Agilent Technologies FS2331 user manual

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The correct logic analyzer sample position for the data valid windows is just to the left of (before) the analyzer clock. This ensures that the data being sent by the controller prior to issuing the strobe is the data sampled by the analyzer. Before moving on to step 3 the sample positions for all data lines should be moved to the left of the clock.

This can be done by grabbing the blue lines on the right side of the clock and dragging them to the left into the proper data valid window. You can grab any of the blue lines on the “stack of channels” or “bus composite” views and all of the sample positionsorfthat label will be adjusted. If a portion of another data valid window appears at the far left of the display and a blue line moves into that window, you can move it to the proper window by expanding the display (as described previously) for the appropriate label and moving the blue line just for the offending signal. After placing the blue lines in the proper data valid window, select the “Results->Set Sample Position to Eye Finder Suggestions” menu pick, and the sample positions will be precisely centered on the proper data valid window for each channel. Since the ECC bits and data mask signals have the same timing as the data lines, their sample positions can be adjusted in a similar way. You can then compress the display if you like.

Setting the sample position for the strobes to the data valid window at the center of the display will cause them to be sampled just after the active edge that caused data to be sampled. Thus, the first transfer of a burst will always show a strobe value of 1, and the last will show a strobe value of 0. This is necessary since for read cycles the strobes are delayed enough that the sample position adjustment range of the analyzer may not be sufficient to sample them before the active edge of the strobe. The sampling strategy for read and write cycles should be consistent to produce consistent output from the analyzer. This does however mean that Data will be sampled before the clock and strobes after the clock (the DataClk signal itself should be sampled before the clock.).

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportLimitation of warranty Product WarrantyExclusive Remedies Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram FS2331 Probe Description Probe Feature SummaryProbe Components DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateProbe Switch Settings Switch # Default factory Function PositionOn closed Connecting the Probe to the Logic Analyzer Logic Analyzer Signal Threshold Voltage SettingsConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems 16753/4/5/6 Logic Analyzer Card RequirementsRecommended Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7
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