Agilent Technologies FS2331 user manual

Page 35

The blue lines show the default logic analyzer sample position. The dark gray areas show periods of time in which the indicated signals are not stable, and the remaining areas indicate where the signals are stable with respect to the clock. The analyzer clock (in this case the command clock computed by differentially receiving CK0 and #CK0) is the time 0 point in the diagram. Several things can be inferred from this diagram:

∙There is a lot of setup and hold time (> 5ns) available to the analyzer to sample information on the command bus.

∙The analyzer clock is a slightly delayed version of CK0 (due to the prop delay of the line receiver on the probe that computes the analyzer clock).

∙The CK0 and #CK0 signals do not seem to transition at exactly the same time. This apparent anomaly (on the order of 200ps) is due to a combination of analyzer threshold error and measurement error in Eye Finder. This shows how Eye Finder may be useful in pointing out areas that deserve closer examination, but care should be used in inferring too much quantitative information from the Eye Finder display.

∙There is no activity on the #Reset line. This is normal for most DDR stimulus.

35

Image 35

Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportExclusive Remedies Product WarrantyLimitation of warranty Logic Analyzer Modules Probe Cable, Connector NumberingIntroduction DefinitionsFS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description DDR Data DDR CommandsProbe Design State Clock GenerationPage Pod Clock Domain Clock Rate Probe Pod AssignmentOn closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 169xx Licensing Setting up the 167xx AnalyzerSetting up the 169xx Analyzer Software Requirements System SoftwareTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Taking a Trace, Triggering, and Seeing Measurement Results Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation State Analysis OperationInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7