Agilent Technologies FS2331 user manual Signal Connections

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Unused Pods	23
Offline Analysis	24
Filtering	25
Timing Analysis Operation	26
Loading the Inverse Assembler and Decoding DDR Commands	26
Taking a Trace, Triggering, and Seeing Measurement Results	26
State Analysis Operation	26
Minimizing intermodule skew	26
The Inverse Assembler and Decoding DDR Commands	27
Taking a Trace, Triggering, and Seeing Measurement Results	27
Tracing the Serial Presence Detect Signals	28
Using Eye Finder with the FS2331 DDR Probe	29
Using EyeScan with the FS2331 Probe	30
Using the FS2331 DDR Probe with an Interposer (FS1024/25)	31
DIMM Signal Loading Option	31
FS2331 Calibration	32
Step 1 – Set Command sample position	34
Step 2 – Write Burst Data Valid Position	37
Step 3 – Read Burst Data Valid Position	41
Step 4 – Adjust the delay line value to maximize R/W overlap	45
Step 5 – Set the final analyzer sample position	45
General Information	47
Probe Interface design capability	47
Standards supported	47
Power requirements	47
Logic Analyzer Requirements	47
Minimum Clock Period	47
Signal Loading	47
Environmental Operating Limits	47
Servicing	47
Signal Connections	48

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportProduct Warranty Limitation of warrantyExclusive Remedies Logic Analyzer Modules Probe Cable, Connector NumberingIntroduction DefinitionsFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components DDR Data DDR CommandsProbe Design State Clock GenerationPage Pod Clock Domain Clock Rate Probe Pod AssignmentSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended 169xx Licensing Setting up the 167xx AnalyzerSetting up the 169xx Analyzer Software Requirements System SoftwareTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Taking a Trace, Triggering, and Seeing Measurement Results Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation State Analysis OperationInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7