Agilent Technologies FS2331 Chip Select Jumper locations, § Isolate the Dedicated DIMM’s pin

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Factory config is J8 pin 1&2 jumpered. This must be removed if J5 connections are used.

Chip Select Jumper locations

2) Dedicating a DIMM slot to the FS2331

This approach offers the highest signal integrity. It involves dedicating a DIMM slot to the FS2331, isolating the Chip Select signals on that DIMM connector from the target’s DDR bus and then wiring active Chip Select signals from all active DIMMs over to the probe’s DIMM connector. Please note that this requires that the appropriate jumpers be placed on J5 per the table above.

The following photos detail this wiring process.

§Isolate the Dedicated DIMM’s pin.

The standard 184 pin DDR DIMM connector has the 4 Chip Select lines routed to the following pins: pin 157 (S0), pin 158 (S1), pin 71 (S2), pin 163 (S3). Most applications will require just S0 single sided DIMMs) or S1 (double-sided DIMMs) to be isolated and jumpered from the active DIMM slot.

Identify the correct pin on the dedicated DIMM slot connector and remove the solder from the pin and hole as shown.

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportProduct Warranty Limitation of warrantyExclusive Remedies Introduction Probe Cable, Connector NumberingDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components Probe Design DDR CommandsState Clock Generation DDR DataPage Pod Clock Domain Clock Rate Probe Pod AssignmentSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended Setting up the 169xx Analyzer Setting up the 167xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7