Agilent Technologies FS2331 Connecting to your Target System Chip Select, If User is dedicating a

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Connecting to your Target System – Chip Select

Many DDR333 systems qualify Command activity using the Chip Select lines, S0:3. This is either because they utilize “2T Timing” in whichheirt control lines (RAS, CAS, WE) may not fully transition to a valid state within one command clock, or because NOP commands are indicated only by releasing all chip selects rather than issuing an actual NOP command. Either of these conditions will make it difficult for the FS2331 to decode Commands properly without valid Chip Select signals.

Because Chip Select (S0:3) signals are routed independently to each DIMM slot and the FS2331 consumes a slot, the probe will not normally be able to see which memory a given command is directed to. As a result the probe cannot properly decode activity on DIMMs that is qualified by these signals unless they are brought to the probe. On some systems this will be seen as small or missing Data eyes after running Eyefinder . This problem can be corrected if the chip select signals for all memory ranks to be traced are made visible to the probe. The FS2331 user has several means for connecting up to 4 different Chip Select signals to the FS2331.

Chip Select Jumpers

The factory configuration of the FS2331 is a single jumper on J8 between pins 1 and 2. This forces S0 low (active) on the FS2331 and effectively qualifies ANY Command seen by the FS2331. This may be sufficient for the proper operation in your target system. If it is not, then there are 3 ways to bring active Chip Select signals to the FS2331. Please note that each of these methods requires all jumpers to be removed from J8.

1) Wiring Chip Select from a DIMM module to the FS2331

Four test points are provided on the DDR probe to allow you to probe Chip Selects from other DIMM slots on the target. You must solder a wire from the DIMM module and connect the wire to the appropriate test point on the FS2331. A table showing jumper configurations is provided. GND points are on J8 pins 2, 4, 6, and 8 to allow the use of twisted pairs . You should keep the wires as short as possible.

 

 

 

If User is dedicating a

Chip Select line

Remove jumper

Connect wire from

DIMM slot, or using an

(factory config)

another DIMM to

Interposer (FS1024 or

 

 

 

 

1025) add

 

 

 

 

S0

J8 pins 1 and 2

J5 pin 2

Jumper J5 pins 1 and 2

 

 

 

 

S1

 

J5 pin 4

Jumper J5 pins 3 and 4

 

 

 

 

S2

 

J5 pin 6

Jumper J5 pins 5 and 6

 

 

 

 

S3

 

J5 pin 8

Jumper J5 pins 7 and 8

 

 

 

 

AnyCS (special)

 

J5 pin 10

Jumper J5 pins 9 and 10

 

 

 

 

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportExclusive Remedies Product WarrantyLimitation of warranty Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateOn closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7
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