Agilent Technologies FS2331 user manual J3 Command and Data

Page 52

J3 Command and Data


		Signal	Logic Analyzer	SAMTEC	SAMTEC	Logic Analyzer	Signal
		Name/Logical	Logic Analyzer	SAMTEC	SAMTEC	Logic Analyzer	name/Logical
		Name/Logical	channel number	Pin number	Pin number	channel number	name/Logical
		Signal name	channel number	Pin number	Pin number	channel number	Signal Name
		Signal name					Signal Name

			Ground	1	2	Ground

			NC	3	4	NC

			Ground	5	6	Ground

		RESETn	Odd D0	7	8	Even D0	CB6

			Ground	9	10	Ground

		FETEN	Odd D1	11	12	Even D1	CB7

			Ground	13	14	Ground

		CKE0	Odd D2	15	16	Even D2	SA2

			Ground	17	18	Ground

		CKE1	Odd D3	19	20	Even D3	WP

			Ground	21	22	Ground

		A13	Odd D4	23	24	Even D4	DQS8

			Ground	25	26	Ground

		A14	Odd D5	27	28	Even D5	DM8/DQS17

			Ground	29	30	Ground

		CK0n	Odd D6	31	32	Even D6	DQ32

			Ground	33	34	Ground

		BA1	Odd D7	35	36	Even D7	DQ36

			Ground	37	38	Ground

		BA0	Odd D8	39	40	Even D8	DQ33

			Ground	41	42	Ground

		WEn	Odd D9	43	44	Even D9	DQ37

			Ground	45	46	Ground

		RASn	Odd D10	47	48	Even D10	DQS4

			Ground	49	50	Ground

		CASn	Odd 11	51	52	Even D11	DM4/DQS13

			Ground	53	54	Ground

		S0n	Odd D12	55	56	Even D12	DQ34

			Ground	57	58	Ground

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportLimitation of warranty Product WarrantyExclusive Remedies Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram FS2331 Probe Description Probe Feature SummaryProbe Components DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateProbe Switch Settings Switch # Default factory Function PositionOn closed Connecting the Probe to the Logic Analyzer Logic Analyzer Signal Threshold Voltage SettingsConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems 16753/4/5/6 Logic Analyzer Card RequirementsRecommended Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7