Agilent Technologies FS2331 Introduction, Definitions, Probe Cable, Connector Numbering

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Introduction

Thank you for purchasing the FuturePlus Systems FS2331 DDR SDRAM Logic Analyzer Probe. We believe you will find the FS2331, along with your Agilent Technologies Logic Analyzer, a valuable tool for helping to characterize and debug your DDR-based systems. This User Manual will provide the information you need to install, configure, and use the FS2331 Probe. If you have any questions about this User Manual or use of the FS2331 Probe, please contact FuturePlus Systems Corporation.

Definitions

DDR Bus Speed

This document will use the following definitions when describing DDR memory speeds:

∙PC1600 or 200Mhz describes DDR DIMMs running at a clock rate on the memory bus differential clock of 100Mhz, which results in a data transfer rate of 200Mhz (or

1.6GBytes/sec throughput). DDR commands are issued at a 100Mhz rate.

∙PC2100 or 266Mhz describes DDR DIMMs running at a clock rate on the memory bus differential clock of 133Mhz, which results in a data transfer rate of 266Mhz (or

2.1GBytes/sec throughput). DDR commands are issued at a 133Mhz rate.

∙PC2700 or 333Mhz describes DDR DIMMs running at a clock rate on the memory bus differential clock of 167Mhz, which results in a data transfer rate of 333Mhz (or

2.7GBytes/sec throughput). DDR commands are issued at a 167Mhz rate.

Probe Cable, Connector Numbering

The FS2331 has 4 connectors that connect to the logic analyzer through 4 logic analyzer adapter cables. These connectors are described as "J1" through "J4". When "Pod <n>" is referenced in this manual it is the logic analyzer cable end that is plugged into "J <n>" of the FS2331 per figure on page 7.

Logic Analyzer Modules

"Module" - A set of logic analyzer cards that have been configured (via internal cables connecting the cards) to operate as a single logic analyzer whose total available channels is the sum of the channels on each card. A trigger within a module can be specified using all of the channels of that module. Each module may be further broken up into "Machines”. A single module may not extend beyond a single 5 card frame.

Logic Analyzer Machines

"Machine" - A set of logic analyzer pods from a logic analyzer module grouped together to operate as a single state or timing analyzer. Each logic analyzer module may be partitioned into up to two independent "Machines" (either two state machines, or a state and a timing machine), and the pods of a module may be assigned freely to either machine. Each state analyzer machine has its own state clock. Turbo mode (333Mhz for 1671x, 400Mhz for 16750/1/2, 600Mhz for 16753/4/5 cards) operation restricts a module to having only one machine. Cross triggering between modules or machines is done via the Intermodule Bus or via the Flag bits, which will communicate across a 16700 frame and its expander, or across multiple frames if the Multiframe product is used.

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportProduct Warranty Limitation of warrantyExclusive Remedies Definitions Probe Cable, Connector NumberingIntroduction Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components State Clock Generation DDR CommandsProbe Design DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended Software Requirements System Software Setting up the 167xx AnalyzerSetting up the 169xx Analyzer 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering State Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7
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