Agilent Technologies FS2331 user manual Timing Analysis Operation, State Analysis Operation

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Timing Analysis Operation

Loading the Inverse Assembler and Decoding DDR Commands

No Inverse Assembler is used for timing analysis. However, symbols are pre-defined for the DDR Command bus. These decode the RAS, CAS, and WE lines to display the DDR Command as “Read”, “Write”, “Precharge”, etc., so you don’t have to refer to the DDR device data sheet to see what command is being executed. Symbols have also been pre-defined for the Read/Write status generated by the probe.

Taking a Trace, Triggering, and Seeing Measurement Results

Timing analysis is the simplest setup, and there are no special factors involved in analyzer trigger setup, initiating a trace, and viewing results. For the Command bus you can use the pre-defined symbols to specify mnemonically the command you wish to trigger on. These are set up by default and are accessible in the trigger tab. The default waveform display also shows DDR Commands mnemonically.

You may setup a trigger, initiate a measurement, and view results in the usual ways via the trigger tab, pressing the run button, and opening the desired display window.

State Analysis Operation

The FS2331 DDR Probe supports the simultaneous 200/266/333Mhz DDR state and 2GHz timing measurement capability of the Agilent Logic Analyzers as well as capture of both Read and Write bursts in a single trace.

The optional calibration procedure documented at the end of this document applies to state measurements only. You may use the 2GHz TimingZoom™ feature at any time during state or timing mode measurements.

Minimizing intermodule skew

The 16700 will automatically time correlate activity on the Command and Data busses. The accuracy of the correlation is typically several nanoseconds, but can be larger. Since even a few nanoseconds is an appreciable fraction of a DDR cycle the DDR Probe provides a mechanism to reduce the skew to approximately one nanosecond using the Intermodule Skew adjustment dialog in the 16700 Intermodule setup window.

To minimize the skew between the logic analyzer channels tracing the Command and Data busses a common signal (Buffered Command Clock) is probed by both analyzers. This signal will have identical timing (within 1ns) as measured by TimingZoom™ when the skew between the Command and Data analyzers is minimized. A detailed procedure to minimize intermodule skew is:

1.Set up the analyzer for state analysis measurements using the procedures described earlier in this User Manual.

2.Make sure that the TimingZoom™ feature is enabled for both the Command and Data analyzers. This is the default when loading a config shipped with the probe.

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportExclusive Remedies Product WarrantyLimitation of warranty Definitions Probe Cable, Connector NumberingIntroduction Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description State Clock Generation DDR CommandsProbe Design DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateOn closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 Software Requirements System Software Setting up the 167xx AnalyzerSetting up the 169xx Analyzer 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering State Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7
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