Agilent Technologies FS2331 user manual Card Configurations for State Analysis

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analyzer cards together to create multi-card modules. You may use modules that are already configured with more than two cards, but only two of the cards (8 pods) will be used for each DDR bus. Remaining pods may be used for any purpose.

Assuming your analyzer cards are installed in slots C and D (slot C being the master), connect the DDR probe cables to the logic analyzer pods as follows for timing analysis measurements:

 

 

 

 

 

 

 

 

FS2331 Conn

Probe Cable

Analyzer Pod

Analyzer Pod

 

 

(J)

 

2 card timing

3 card state

 

 

 

 

 

 

 

 

configuration

configuration

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J1 Odd

Pod 1

A1

A1 (master 1)

 

 

 

 

 

 

 

 

J1 Even

Pod 2

A2

A2

 

 

J2 Odd

Pod 3

A3

B1

 

 

J2 Even

Pod 4

A4

C2 (master 2)

 

 

J3 Odd

Pod 5

B1

C1

 

 

J3 Even

Pod 6

B2

B2

 

 

J4 Odd

Pod 7

B3

B3

 

 

J4 Even

Pod 8

B4

B4

 

 

 

 

 

 

169xx users please refer to the “Setting up the 16900 Analyzer” section of this manual on the use of the define probes feature to determine how to attach the logic analyzer to the probe

If your analyzer is in slots other than these, adjust the pod connections accordingly. The probe cables indicated above as connecting to slot C pods should connect to the pods of the master slot of your analyzer. The remaining pod cables should be connected to the pods of the next higher slot. If you must connect to pods in some other fashion, then you will have to modify the configuration file accordingly.

Load the logic analyzer configuration file for timing (see configuration file table) into the master slot of your analyzer. It doesn't matter whether you select to load "Configs only" or "Configs and Data".

You are now ready to start making measurements. See the section “Timing Analysis Operation” for information on making timing measurements.

3 card Configurations for State Analysis

The three cards used for state analysis must be configured as two separate logic analyzer modules. The card in slot C is set up as a single card module for tracing DDR Commands and the card in slots A and B must be set up as a single two card module for tracing DDR Data. Slot A holds the master card. You may use a module with more than one card for capturing Commands and more than two cards for capturing Data, but only a subset of each modules pods will then be used by the DDR probe. You may also place the cards in slots other than described here, but must then adjust the pod connection tables and configuration file loading instructions accordingly.

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportProduct Warranty Limitation of warrantyExclusive Remedies Definitions Probe Cable, Connector NumberingIntroduction Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components State Clock Generation DDR CommandsProbe Design DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6 Recommended Software Requirements System Software Setting up the 167xx AnalyzerSetting up the 169xx Analyzer 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering State Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7
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