Agilent Technologies FS2331 user manual Buffcmdclk

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		Signal	Logic Analyzer	SAMTEC	SAMTEC	Logic Analyzer	Signal
		Name/Logical	Logic Analyzer	SAMTEC	SAMTEC	Logic Analyzer	name/Logical
		Name/Logical	channel number	Pin number	Pin number	channel number	name/Logical
		Signal name	channel number	Pin number	Pin number	channel number	Signal Name
		Signal name					Signal Name

		S1n	Odd D13	59	60	Even D13	DQ38

			Ground	61	62	Ground

		S2n	Odd D14	63	64	Even D14	DQ35

			Ground	65	66	Ground

		S3n	Odd D15	67	68	Even D15	DQ39

			Ground	69	70	Ground

			NC	71	72	NC

			Ground	73	74	Ground

			NC	75	76	NC

			Ground	77	78	Ground

		BUFFCMDCLK	Odd D16P/Odd	79	80	Even DP16P/Even	BUFFCMDCLK
		BUFFCMDCLK	CLKN	79	80	CLKN	BUFFCMDCLK
			CLKN			CLKN
			Ground	81	82	Ground

		Ground	Odd DP16N/Odd	83	84	Even DP16N/Even	Ground
		Ground	CLKN	83	84	CLKN	Ground
			CLKN			CLKN
			Ground	85	86	Ground

			Odd External Ref	87	88	Even External Ref

			Ground	89	90	Ground

			NC	91	92	NC

			Ground	93	94	Ground

			Ground	95	96	Ground

		+5V	+5V	97	98	+5V	+5V

		+5V	+5V	99	100	+5V	+5V

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportExclusive Remedies Product WarrantyLimitation of warranty Introduction Probe Cable, Connector NumberingDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description Probe Design DDR CommandsState Clock Generation DDR DataPage Pod Clock Domain Clock Rate Probe Pod AssignmentOn closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 Setting up the 169xx Analyzer Setting up the 167xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7