Agilent Technologies FS2331 user manual Adjust the delay line value to maximize R/W overlap

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Step 4 – Adjust the delay line value to maximize R/W overlap

You can use the following formula to calculate the proper value for the read delay line that will maximize overlap between read and write data valid windows:

New U18 Delay Line Value = Current U18 Delay Line Value + (Avg. Read Position – Avg. Write Position)

For this example the formula yields:

1400ps = 1200ps + (-2250ps – (-2450ps))

Note that the negative sample position values as indicated in the Eye Finder display are used in the equation above.

At this point you should not replace the delay line in the “U18” position with the 1700ps value. Keep in mind the +/-50ps tolerance of the delay lines when adjusting them since that can cause the actual delay change to be +/-100ps different from the desired adjustment.

Step 5 – Set the final analyzer sample position

Once the delay line value has been adjusted you are ready to run Eye Finder to set the final sample position for the logic analyzer to use when capturing both read and write bursts (SW 6 OFF). To perform this final step you should set the probe configuration switches to clock both read and write bursts to the analyzer, start your stimulus (that contains frequent read and write bursts), and run Eye Finder.

After the EyeFinder process is complete. Inspect the DataClock and all Data windows. Insure that the sampling position (blue line) is set to the middle of the light gray window (eye). If they are not they can be moved independently to place them in the middle of each eye.

The following is a typical resultant display:

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportProduct Warranty Limitation of warrantyExclusive Remedies Introduction Probe Cable, Connector NumberingDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components Probe Design DDR CommandsState Clock Generation DDR DataPage Pod Clock Domain Clock Rate Probe Pod AssignmentSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended Setting up the 169xx Analyzer Setting up the 167xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7