Agilent Technologies FS2331 user manual

Page 46

Notice in this display the data valid windows are reduced in size. This is because the measured windows represent the intersection of the read and write windows.

Notice also that there is almost no data valid window for the strobes. This is unavoidable since the timing of the strobes still shift one quarter clock cycle between read and write bursts. The data valid window thus shrinks to the natural overlap of the strobe timings. Signal jitter in real systems usually reduce the window size to zero. Without the separate analyzer clock timing adjustment for read and write bursts the data valid window for all data lines would look very much like the strobes.

46

Image 46

Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportLimitation of warranty Product WarrantyExclusive Remedies Definitions Probe Cable, Connector NumberingIntroduction Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram FS2331 Probe Description Probe Feature SummaryProbe Components State Clock Generation DDR CommandsProbe Design DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateProbe Switch Settings Switch # Default factory Function PositionOn closed Connecting the Probe to the Logic Analyzer Logic Analyzer Signal Threshold Voltage SettingsConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems 16753/4/5/6 Logic Analyzer Card RequirementsRecommended Software Requirements System Software Setting up the 167xx AnalyzerSetting up the 169xx Analyzer 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering State Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7