Agilent Technologies FS2331 user manual Signal Connections J1 Data, Samtec

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Signal Connections

J1 Data


		Signal	Logic Analyzer	SAMTEC	SAMTEC	Logic Analyzer	Signal
		Name/Logical	Logic Analyzer	SAMTEC	SAMTEC	Logic Analyzer	name/Logical
		Name/Logical	channel number	Pin number	Pin number	channel number	name/Logical
		Signal name	channel number	Pin number	Pin number	channel number	Signal Name
		Signal name					Signal Name

			Ground	1	2	Ground

			NC	3	4	NC

			Ground	5	6	Ground

		DQ0	Odd D0	7	8	Even D0	DQ4

			Ground	9	10	Ground

		DQ1	Odd D1	11	12	Even D1	DQ5

			Ground	13	14	Ground

		DQS0	Odd D2	15	16	Even D2	DM0/DQS9

			Ground	17	18	Ground

		DQ2	Odd D3	19	20	Even D3	DQ6

			Ground	21	22	Ground

		DQ3	Odd D4	23	24	Even D4	DQ7

			Ground	25	26	Ground

		DQ8	Odd D5	27	28	Even D5	DQ12

			Ground	29	30	Ground

		DQ9	Odd D6	31	32	Even D6	DQ13

			Ground	33	34	Ground

		DQS1	Odd D7	35	36	Even D7	DM1/DQS10

			Ground	37	38	Ground

		DQ10	Odd D8	39	40	Even D8	DQ14

			Ground	41	42	Ground

		DQ11	Odd D9	43	44	Even D9	DQ15

			Ground	45	46	Ground

		DQ16	Odd D10	47	48	Even D10	DQ20

			Ground	49	50	Ground

		DQ17	Odd 11	51	52	Even D11	DQ21

			Ground	53	54	Ground

		DQS2	Odd D12	55	56	Even D12	DM2/DQS11

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportProduct Warranty Limitation of warrantyExclusive Remedies Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7