Agilent Technologies FS2331 user manual Switch # Default factory Function Position, On closed

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Probe Switch Settings

A switch bank of 6 independent SPST switches is provided on the FS2331 for user selection of a number of probe features. These are detailed below.

	Switch #		Default (factory	Function
			position)

		1	Open	Not available

		2	Open	Not available

		3	Open	Not available

				When SW4 is closed the Buffered
				Command Clock signal to the logic
		4	Open	analyzer is passed only when there is a
	CS_Gate_CK0		Open	valid (low) S0:3 signal to the probe. This
	CS_Gate_CK0			valid (low) S0:3 signal to the probe. This
				is useful for EyeScan of Command
				signals.

				SW5 is dependent on SW6. When SW6
	5.	Write or		is open, SW5 open will pass a state
	5.	Write or	Open	clock signal only during a Read
	Read Only		Open	clock signal only during a Read
	Read Only			command. SW5 closed will pass only
				command. SW5 closed will pass only
				on a Write.

				When SW6 is closed, the probe
	6	R/W Filter	Closed	provides a state clock during both
	6	R/W Filter	Closed	Reads and Writes. When SW6 is open
				Reads and Writes. When SW6 is open
				it engages SW5.

ON (closed)

1 2

3

4 5

6

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportProduct Warranty Limitation of warrantyExclusive Remedies Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7