Agilent Technologies FS2331 user manual Write Burst Data Valid Position

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Notice that this measurement was taken with one of the Chip Select lines hooked up. You can see that its data valid window is smaller than that of the other command bus signals. This is due largely to the use of soldered wires to connect the Chip Select signal. Eye Finder provides a convenient way to make sure that the wires you use to connect to the Chip Select test points are not too long to get a valid indication of which DIMM is selected (or to make sure that signal integrity for the Chip Select signal is not overly compromised).

Step 2 – Write Burst Data Valid Position

For this step DDR bus activity must include a high rate of write bursts. Memory tests or video clips are usually a good source of such activity. To measure the write burst data valid position, start the stimulus on the DDR bus. In most cases the stimulus will contain a mix of read and write cycles. If this is the case, you must set the switches on the DDR probe to select only write bursts to be clocked into the analyzer (SW-6 ON, SW-5 OFF).

Open the Eye Finder control panel on the logic analyzer capturing data. Run Eye Finder and note the results. Depending on the density of bursts in the stimulus you may find that Eye Finder could take quite a while to run. In general, the denser the bursts the less time Eye Finder needs to complete its work. If the density is too low then Eye Finder may take as much as 30 minutes or more to run, or may terminate within a few seconds and report that not enough clocks occurred within a 5 second interval to make a good measurement. If this happens you can open the “Eye Finder->Advanced” dialog and select the “Short” run option. You can also try new stimulus or turn the cache off on your processor to increase burst density.

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportLimitation of warranty Product WarrantyExclusive Remedies Introduction Probe Cable, Connector NumberingDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram FS2331 Probe Description Probe Feature SummaryProbe Components Probe Design DDR CommandsState Clock Generation DDR DataPage Pod Clock Domain Clock Rate Probe Pod AssignmentProbe Switch Settings Switch # Default factory Function PositionOn closed Connecting the Probe to the Logic Analyzer Logic Analyzer Signal Threshold Voltage SettingsConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems 16753/4/5/6 Logic Analyzer Card RequirementsRecommended Setting up the 169xx Analyzer Setting up the 167xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Timing Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7
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