Texas Instruments TMS320 Apac, LPH ², Lta, LTP ², LTS ², MAC ², Macd ², Mpya ³, Mpyk, MPYS³

Page 14

TMS320C25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Table 3. TMS320C25 Instruction Set Summary (continued)

 

 

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS

 

 

 

 

 

 

 

 

 

 

MNEMONIC

DESCRIPTION

NO.

 

 

 

 

INSTRUCTION BIT CODE

 

 

 

 

 

WORDS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

APAC

Add P register to accumulator

1

1

1

0

0

1

1

1

0

0

0

0

1

0

1

0

1

LPH²

Load high P register

1

0

1

0

1

0

0

1

1

I

 

 

 

D

 

 

 

LT

Load T register

1

0

0

1

1

1

1

0

0

I

 

 

 

D

 

 

 

LTA

Load T register and accumulate previous product

1

0

0

1

1

1

1

0

1

I

 

 

 

D

 

 

 

LTD

Load T register, accumulate previous product,

1

0

0

1

1

1

1

1

1

I

 

 

 

D

 

 

 

and move data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LTP²

Load T register and store P register in

1

0

0

1

1

1

1

1

0

I

 

 

 

D

 

 

 

accumulator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LTS²

Load T register and subtract previous product

1

0

1

0

1

1

0

1

1

I

 

 

 

D

 

 

 

MAC²

Multiply and accumulate

2

0

1

0

1

1

1

0

1

I

 

 

 

D

 

 

 

MACD²

Multiply and accumulate with data move

2

0

1

0

1

1

1

0

0

I

 

 

 

D

 

 

 

MPY

Multiply (with T register, store product in

1

0

0

1

1

1

0

0

0

I

 

 

 

D

 

 

 

P register)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MPYA³

Multiply and accumulate previous product

1

0

0

1

1

1

0

1

0

I

 

 

 

D

 

 

 

MPYK

Multiply immediate

1

1

0

1

 

 

 

 

 

 

K

 

 

 

 

 

 

MPYS³

Multiply and subtract previous product

1

0

0

1

1

1

0

1

1

I

 

 

 

D

 

 

 

MPYU³

Multiply unsigned

1

1

1

0

0

1

1

1

1

I

 

 

 

D

 

 

 

PAC

Load accumulator with P register

1

1

1

0

0

1

1

1

0

0

0

0

1

0

1

0

0

SPAC

Subtract P register from accumulator

1

1

1

0

0

1

1

1

0

0

0

0

1

0

1

1

0

SPH³

Store high P register

1

0

1

1

1

1

1

0

1

I

 

 

 

D

 

 

 

SPL³

Store low P register

1

0

1

1

1

1

1

0

0

I

 

 

 

D

 

 

 

SPM²

Set P register output shift mode

1

1

1

0

0

1

1

1

0

0

0

0

0

1

0

PM

SQRA²

Square and accumulate

1

0

0

1

1

1

0

0

1

I

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SQRS²

Square and subtract previous product

1

0

1

0

1

1

0

1

0

I

 

 

 

D

 

 

 

²These instructions are not included in the TMS320C1x instruction set. ³ These instructions are not included in the TMS32020 instruction set.

14

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-ChipPackage ArchitectureTMS320 Second-Generation Device Overview TypeFunctional block diagram TMS320C2x SECOND-GENERATION Devices16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory controlTMS320 SECOND-GENERATION Devices Memory MapsMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZACLTA ApacLPH ² LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation supportParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAXHold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timingTiming Diagrams Clock timingReady Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Holda Hold timing part aHold ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsParameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationEPT Pin Nomenclature TMS320E25VCC EPT VPPProgram Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal ErasureFast Programming Flowchart Program verifyROM protection and verification Output disableRead VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice
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