Texas Instruments specifications Typical Supply Current Characteristics for TMS320C25

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TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25

ICC vs f(CLKIN) and VCC

ICC vs f(CLKIN) and VCC

Normal Operating Mode

Powerdown Mode

ICC, mA

170

160TA = 25°C

140

130

120

110

100

90

80

70

60

50

40

30

20

10

48 12 16 20 24 28 32 36 40 44 48 52 f(CLKIN), MHz

VCC = 5.50 V VCC = 5.25 V VCC = 5.00 V VCC = 4.75 V VCC = 4.50 V

ICC, mA

80

70

60

50

40

30

20

10

0

48 12 16 20 24 28 32 36 40 44 48 52 f(CLKIN), MHz

VCC = 5.50 V VCC = 5.25 V VCC = 5.00 V VCC = 4.75 V VCC = 4.50 V

ADVANCE INFORMATION

TMS320C25FNL (PLCC) reflow soldering precautions

Recent tests have identified an industry-wide problem experienced by surface mounted devices exposed to reflow soldering temperatures. This problem involves a package cracking phenomenon sometimes experienced by large (e.g., 68-lead) plastic leaded chip carrier (PLCC) packages during surface mount manufacturing. This phenomenon occur if the TMS320C25FNL is exposed to uncontrolled levels of humidity prior to reflow solder. This moisture can flash to steam during solder reflow, causing sufficient stress to crack the package and compromise device integrity. If the TMS320C25FNL is being socketed, no special handling precautions are required. In addition, once the device is soldered into the board, no special handling precautions are required.

In order to minimize moisture absorption, TI ships the TMS320C25FNL in ªdry packº shipping bags with a RH indicator card and moisture-absorbing desiccant. These moisture-barrier shipping bags will adequately block moisture transmission to allow shelf storage for 12 months from date of seal when stored at less than 60% relative humidity (RH) and less than 30°C. Devices may be stored outside the sealed bags indefinitely if stored at less than 25% RH and 30°C.

Once the bag seal is broken, the devices should be stored at less than 60% RH and 30°C as well as reflow soldered within two days of removal. In the event that either of the above conditions is not met, TI recommends these devices be baked in a clean oven at 125°C and 10% maximum RH for 24 hours. This restores the devices to their ªdry packedº moisture level.

NOTE

Shipping tubes will not withstand the 125°C baking process. Devices should be transferred to a metal tray or tube be- fore baking. Standard ESD precautions should be followed.

In addition, TI recommends that the reflow process not exceed two solder cycles and the temperature not exceed 220°C.

If you have any additional questions or concerns, please contact your local TI representative.

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionSignals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-ChipPackage ArchitectureTMS320 Second-Generation Device Overview TypeFunctional block diagram TMS320C2x SECOND-GENERATION Devices16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory controlTMS320 SECOND-GENERATION Devices Memory MapsInterrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZACLTA ApacLPH ² LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Specification overview Documentation supportRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitRS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAXHold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timingTiming Diagrams Clock timingMemory read timing BR, PS, D SReady Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Holda Hold timing part aHold ExecuteHold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsMechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationEPT Pin Nomenclature TMS320E25VCC EPT VPPProgram Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal ErasureFast Programming Flowchart Program verifyOutput disable ReadROM protection and verification VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice
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