Texas Instruments TMS320E25 Programming Mode Levels, Erasure, Fast programming, Signal

Page 60

TMS320E25

ADVANCE INFORMATION

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Table 5 shows the programming levels required for programming, verifying and reading the EPROM cell. The paragraphs following the table describe the function of each programming level.

Table 5. TMS320E25 Programming Mode Levels

SIGNAL

TMS320E25

TMS27C64

PROGRAM

PROGRAM

PROGRAM

 

READ

OUTPUT

NAME ²

PIN

PIN

VERIFY

INHIBIT

 

DISABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

20

 

VIL

 

VIL

VIH

 

VIL

VIL

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

42

22

 

VIH

 

 

 

X

 

 

 

VIH

 

 

 

G

 

 

 

 

 

PULSE

 

 

PULSE

 

 

 

 

 

 

 

 

 

41

27

 

 

 

 

VIH

X

 

VIH

VIH

 

PGM

 

 

PULSE

 

 

 

 

VPP

25

1

 

VPP

 

VPP

VPP

 

VCC

VCC

 

VCC

61,35

28

VCC + 1

VCC + 1

VCC + 1

 

VCC

VCC

 

VSS

27,44,10

14

 

VSS

 

VSS

VSS

 

VSS

VSS

CLKIN

52

14

 

VSS

 

VSS

VSS

 

VSS

VSS

 

 

 

 

 

 

 

 

65

14

 

VSS

 

VSS

VSS

 

VSS

VSS

 

 

RS

 

 

 

 

 

EPT

24

26

 

VSS

 

VSS

VSS

 

VSS

VSS

Q1-Q8

18-11

11-13,15-19

 

DIN

 

QOUT

HI-Z

 

QOUT

HI-Z

A12-A10

40-38

2,23,21,

 

ADDR

 

ADDR

X

 

ADDR

X

 

 

 

 

 

 

 

 

 

 

 

A9-A7

37,36,34

24,25,3

 

ADDR

 

ADDR

X

 

ADDR

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

33

4

 

ADDR

 

ADDR

X

 

ADDR

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

32

5

 

ADDR

 

ADDR

X

 

ADDR

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

31

3

 

ADDR

 

ADDR

X

 

ADDR

X

 

 

 

 

 

 

 

 

 

 

 

A3-A0

30-28,26

7-10

 

ADDR

 

ADDR

X

 

ADDR

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

²In accordance with TMS27C64.

LEGEND;

VIH = TTL high level; VIL = TTL low level; ADDR = byte address bit

±0.5 V; VCC = 5 ± 0.25 V; X = don't careVPP = 12.5 V

PULSE = low-going TTL level pulse; DIN = byte to be programmed at ADDR

QOUT = byte stored at ADDR; RBIT = ROM protect bit.

erasure

Before programming, the device is erased by exposing the chip through the transparent lid to high-intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV-intensity ⋅ exposure-time) is 15 W•s/cm2. A typical 12 mW/cm2, filterless UV lamp will erase the device in 21 minutes. The lamp should be located approximately 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. Note that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS320E25, the window should be covered with an opaque label.

fast programming

After erasure (all memory bits in the cell are logic one), logic zeroes are programmed into the desired locations. The fast programming algorithm, shown in Figure 10, is normally used to program the entire EPROM contents, although individual locations may be programmed separately. A programmed logic zero can be erased only by ultraviolet light. Data is presented in parallel (eight bits) on pins Q8-Q1. Once addresses and data are stable, PGM is pulsed. The programming mode is achieved when VPP = 12.5 V, PGM = VIL, VCC = 6 V, G = VIH, and E = VIL More than one TMS320E25 can be programmed when the devices are connected in parallel. Locations can be programmed in any order.

Programming uses two types of programming pulses: prime and final. The length of the prime pulse is 1 ms. After each prime pulse, the byte being programmed is verified. If correct data is read, the final programming pulse is applied; if correct data is not read, an additional 1-ms prime pulse is applied up to a maximum of 15 times. The final programming pulse is 4 ms times the number of prime programming pulses applied. This sequence of programming and verification is performed at VCC = 6 V, and VPP = 12.5 V. When the full fast programming routine is complete, all bits are verified with VCC = VPP = 5 V.

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionSignals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Key Features TMS32020 Bit-Reversed Indexed-Addressing Mode forMemory Space Wait States for Communication to Slower Off-ChipArchitecture TMS320 Second-Generation Device OverviewPackage TypeFunctional block diagram TMS320C2x SECOND-GENERATION DevicesTimer Scaling shifter16 ⋅ 16-bit parallel multiplier Memory controlTMS320 SECOND-GENERATION Devices Memory MapsInterrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary SUBT² XORXORK² ZACApac LPH ²LTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Specification overview Documentation supportRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitRS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing Eprom Programming See Notes 14VPP IPP1INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Contrast Summary of Electrical Specifications Clock characteristics and timingParameter MIN TYP MAXMemory and peripheral interface timing RS, INT, BIO, and XF timingHold timing Serial port timingTiming Diagrams Clock timingMemory read timing BR, PS, D SReady Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Hold timing part a HoldHolda ExecuteHold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsMechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationPin Nomenclature TMS320E25 VCCEPT EPT VPPTMS320E25 Programming Mode Levels SignalProgram Read Output Name ² PIN Verify Inhibit Disable ErasureFast Programming Flowchart Program verifyOutput disable ReadROM protection and verification TMS320E25 Protect and Verify Eprom Mode Levels Eprom protectVIH VIL PGM VPP VCC VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice
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