Texas Instruments TMS320 specifications Advance

Page 56

TMS320C25

TMS320C25-50

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

68-lead plastic leaded chip carrier package (TMS320C25 and TMS320C25-50)

 

 

 

 

 

 

Seating

 

 

 

 

 

 

 

Plane

1,27 (0.050) T.P.

 

 

 

 

 

 

 

 

 

 

 

 

0,25 (0.010) R Max

 

(see Note B)

 

 

 

 

 

 

 

 

 

 

 

 

 

3 Places

 

 

 

 

24,33 (0.956)

 

 

 

 

 

 

 

24,13 (0.950)

 

 

 

 

23,62 (0.930)

 

(see Note A)

 

 

 

 

 

 

 

 

 

23,11 (0.910)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(At Seating Plane)

 

25,27 (0.995)

 

 

 

 

 

 

 

 

25,02 (0.985)

 

 

 

 

 

 

 

ADVANCE

 

 

 

 

 

 

0,94 (0.037)

 

 

 

1,22 (0.048)

 

 

0,69 (0.027) R

 

 

 

⋅ 45°

 

 

 

 

 

 

1,07 (0.042)

 

1,35 (0.053)

⋅ 45°

 

 

24,33 (0.956)

 

 

1,19 (0.047)

 

 

 

 

 

INFORMATION

 

 

24,13 (0.950)

 

 

2,79 (0.110)

 

 

 

(see Note A)

 

 

 

 

 

 

 

2,41 (0.095)

 

 

 

 

 

 

 

 

 

 

25,27 (0.995)

 

 

4,50 (0.177)

 

 

 

25,02 (0.985)

 

 

 

 

 

 

 

4,24 (0.167)

 

 

 

 

 

 

 

 

Thermal Resistance Characteristics

0,81 (0.032)

1,52 (0.060)

 

0,66 (0.026)

Min

 

 

 

 

 

 

 

 

 

PARAMETER

MAX

UNIT

 

 

 

 

RθJA

Junction-to-free-air

46

°C/W

 

0,64 (0.025)

 

 

 

 

 

thermal resistance

 

 

 

 

 

 

 

 

Min

 

 

 

RθJC

Junction-to-case

11

°C/W

 

 

 

 

 

thermal resistance

 

 

 

 

 

 

 

 

 

0,51 (0.020)

 

 

 

 

 

 

 

 

0,36 (0.014)

 

 

 

 

 

 

 

 

Lead Detail

 

 

 

 

 

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

 

NOTES: A. Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by this dimension. B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.

WARNING

When reflow soldering is required, refer to page 54 for special handling instructions.

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

Page 55 Page 57
Image 56
Page 55 Page 57
Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Key Features TMS32020 Bit-Reversed Indexed-Addressing Mode forMemory Space Wait States for Communication to Slower Off-ChipArchitecture TMS320 Second-Generation Device OverviewPackage TypeFunctional block diagram TMS320C2x SECOND-GENERATION DevicesTimer Scaling shifter16 ⋅ 16-bit parallel multiplier Memory controlTMS320 SECOND-GENERATION Devices Memory MapsMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary SUBT² XORXORK² ZACApac LPH ²LTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation supportParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing Eprom Programming See Notes 14VPP IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Contrast Summary of Electrical Specifications Clock characteristics and timingParameter MIN TYP MAXMemory and peripheral interface timing RS, INT, BIO, and XF timingHold timing Serial port timingTiming Diagrams Clock timingReady Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Hold timing part a HoldHolda ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsParameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationPin Nomenclature TMS320E25 VCCEPT EPT VPPTMS320E25 Programming Mode Levels SignalProgram Read Output Name ² PIN Verify Inhibit Disable ErasureFast Programming Flowchart Program verifyROM protection and verification Output disableRead TMS320E25 Protect and Verify Eprom Mode Levels Eprom protectVIH VIL PGM VPP VCC VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice
Top Page Image Contents