Texas Instruments TMS320 PGA and PLCC/CER-QUAD PIN Assignments, Function PIN, Signals Definition

Page 2

TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

PGA AND PLCC/CER-QUAD PIN ASSIGNMENTS

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

FUNCTION

PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

K1/26

 

A12

K8/40

D2

E1/16

 

D14

A5/3

 

 

 

 

 

 

 

 

 

 

 

 

 

H1/22

VCC

H2/23

 

 

 

INT2

 

 

 

 

 

A1

K2/28

 

A13

L9/41

D3

D2/15

 

D15

B6/2

 

 

 

 

 

 

 

 

 

 

 

 

 

J11/46

VCC

L6/35

 

 

 

IS

 

 

 

 

 

 

 

 

 

 

A2

L3/29

 

A14

K9/42

D4

D1/14

 

DR

J1/24

 

 

 

 

 

 

 

 

 

 

 

 

²

A6/1

VSS

B1/10

 

 

 

MP/MC

A3

K3/30

 

A15

L10/43

D5

C2/13

 

 

 

 

 

 

 

K10/45

 

 

 

 

 

 

 

 

 

 

 

 

 

C10/59

VSS

K11/44

 

 

DS

 

 

 

 

 

 

MSC

 

 

 

A4

L4/31

 

 

 

 

B7/68

D6

C1/12

 

DX

E11/54

 

 

 

 

 

 

 

 

 

 

 

 

 

J10/47

VSS

L2/27

 

BIO

 

 

 

PS

 

 

 

 

 

A5

K4/32

 

 

 

 

G11/50

D7

B2/11

 

FSR

J2/25

 

READY

B8/66

XF

D11/56

 

BR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A6

L5/33

 

CLKOUT1

C11/58

D8

A2/9

 

FSX

F10/53

 

 

 

 

 

 

 

 

 

 

 

 

 

A8/65

X1

G10/51

 

 

 

RS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

K5/34

 

CLKOUT2

D10/57

D9

B3/8

 

 

 

 

 

 

 

A7/67

 

 

 

 

 

 

 

 

 

 

 

 

 

H11/48

X2/CLKIN

F11/52

 

 

HOLD

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A8

K6/36

 

CLKR

B9/64

D10

A3/7

 

 

 

 

 

 

 

E10/55

 

 

 

 

 

 

 

 

 

 

 

 

 

H10/49

 

 

 

 

HOLDA

 

 

STRB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A9

L7/37

 

CLKX

A9/63

D11

B4/6

 

 

 

 

 

 

 

B11/60

 

 

 

 

 

 

 

 

 

 

 

 

 

F2/19

 

 

 

 

IACK

 

 

SYNC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A10

K7/38

 

D0

F1/18

D12

A4/5

 

 

 

 

 

 

 

G1/20

 

VCC

A10/61

 

 

 

 

INT0

 

 

 

 

A11

L8/39

 

D1

E2/17

D13

B5/4

 

 

 

 

 

 

 

G2/21

 

VCC

B10/62

 

 

 

 

INT1

 

 

 

 

²On the TMS32020, MP/MC must be connected to VCC.

 

 

SIGNALS

I/O/Z³

DEFINITION

 

VCC

I

5-V supply pins

 

VSS

I

Ground pins

 

X1

O

Output from internal oscillator for crystal

 

X2/CLKIN

I

Input to internal oscillator from crystal or external clock

 

CLKOUT1

O

Master clock output (crystal or CLKIN frequency/4)

 

CLKOUT2

O

A second clock output signal

 

D15-D0

I/O/Z

16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data, and I/O spaces.

 

A15-A0

O/Z

16-bit address bus A15 (MSB) through A0 (LSB)

 

PS,

 

 

 

 

DS,

 

 

 

IS

 

O/Z

Program, data, and I/O space select signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O/Z

Read/write signal

 

R/W

 

STRB

 

 

 

 

 

O/Z

Strobe signal

 

RS

 

 

 

 

 

 

 

 

 

 

I

Reset input

 

INT2

-

INT0

 

I

External user interrupt inputs

 

 

 

 

 

 

 

 

 

I

Microprocessor/microcomputer mode select pin

 

MP/MC

 

MSC

 

 

 

 

O

Microstate complete signal

 

IACK

 

 

 

O

Interrupt acknowledge signal

 

READY

I

Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is complete.

 

BR

 

 

 

 

O

Bus request signal. Asserted when the TMS320C2x requires access to an external global data memory space.

 

XF

O

External flag output (latched software-programmable signal)

 

HOLD

 

 

I

Hold input. When asserted, TMS320C2x goes into an idle mode and places the data, address, and control lines in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the high impedance state.

 

HOLDA

 

O

Hold acknowledge signal

 

SYNC

 

I

Synchronization input

 

BIO

 

I

Branch control input. Polled by BIOZ instruction.

 

DR

I

Serial data receive input

 

CLKR

I

Clock for receive input for serial port

 

FSR

I

Frame synchronization pulse for receive input

 

DX

O/Z

Serial data transmit output

 

CLKX

I

Clock for transmit output for serial port

 

FSX

I/O/Z

Frame synchronization pulse for transmit. Configuration as either an input or an output.

³ I/O/Z denotes input/output/high-impedance state.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

Page 1 Page 3
Image 2
Page 1 Page 3
Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-ChipPackage ArchitectureTMS320 Second-Generation Device Overview TypeFunctional block diagram TMS320C2x SECOND-GENERATION Devices16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory controlTMS320 SECOND-GENERATION Devices Memory MapsMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZACLTA ApacLPH ² LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation supportParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAXHold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timingTiming Diagrams Clock timingReady Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Holda Hold timing part aHold ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsParameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationEPT Pin Nomenclature TMS320E25VCC EPT VPPProgram Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal ErasureFast Programming Flowchart Program verifyROM protection and verification Output disableRead VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice
Top Page Image Contents