Texas Instruments Architecture, TMS320 Second-Generation Device Overview, Package, Type

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TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Table 1 provides an overview of the second-generation TMS320 processors with comparisons of memory, I/O, cycle timing, power, package type, technology, and military support. For specific availability, contact the nearest TI Field Sales Office.

Table 1. TMS320 Second-Generation Device Overview

 

 

 

MEMORY

 

 

 

I/O²

 

 

CYCLE

TYP

 

PACKAGE

DEVICE

 

 

ON-CHIP

 

OFF-CHIP

 

 

 

TIMER

TIME

POWER

 

TYPE

 

 

 

 

 

 

 

 

 

 

 

RAM

ROM/EPROM

PROG DATA

 

 

 

 

(ns)

(mW)

 

 

 

 

 

SER

PAR

DMA

 

PGA

PLCC

CER-QUAD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS32020³

(NMOS)

544

Ð

 

64K

64K

YES

16 ⋅ 16

YES

YES

200

1250

68

Ð

Ð

TMS320C25³

(CMOS)

544

4K

 

64K

64K

YES

16 ⋅ 16

CON

YES

100

500

68

68

Ð

TMS320C25-50§

(CMOS)

544

4K

 

64K

64K

YES

16 ⋅ 16

CON

YES

80

500

Ð

68

Ð

TMS320E25§

(CMOS)

544

4K

 

64K

64K

YES

16 ⋅ 16

CON

YES

100

500

Ð

Ð

68

²SER = serial; PAR = parallel; DMA = direct memory access; CON = concurrent DMA. ³ Military version available; contact nearest TI Field Sales Office for availability.

§ Military version planned; contact nearest TI Field Sales Office for details.

architecture

The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory lie in two separate spaces, permitting a full overlap of instruction fetch and execution. The TMS320 family's modification of the Harvard architecture allows transfers between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values.

Increased throughput on the TMS320C2x devices for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing.

The architectural design of the TMS320C2x emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations.

32-bit ALU/accumulator

The 32-bit Arithmetic Logic Unit (ALU) and accumulator perform a wide range of arithmetic and logical instructions, the majority of which execute in a single clock cycle. The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bit in a word. These instructions provide the following capabilities:

•

•

•

Branch to an address specified by the accumulator

Normalize fixed-point numbers contained in the accumulator

Test a specified bit of a word in data memory

One input to the ALU is always provided from the accumulator, and the other input may be provided from the Product Register (PR) of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus. After the ALU has performed the arithmetic or logical operations, the result is stored in the accumulator.

The 32-bit accumulator is split into two 16-bit segments for storage in data memory. Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage. The contents of the accumulator remain unchanged.

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-ChipTMS320 Second-Generation Device Overview ArchitecturePackage TypeSECOND-GENERATION Devices Functional block diagram TMS320C2xScaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory controlMemory Maps TMS320 SECOND-GENERATION DevicesMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZACLPH ² ApacLTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Documentation support Specification overviewParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAXRS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timingClock timing Timing DiagramsReady Memory read timingBR, PS, D S CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Hold Hold timing part aHolda ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellVCC Pin Nomenclature TMS320E25EPT EPT VPPSignal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable ErasureProgram verify Fast Programming FlowchartROM protection and verification Output disableRead Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPPRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice
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