Texas Instruments TMS320 specifications TdC1L-AL Low after CLKOUT1 low

Page 31

TMS320C25, TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

RS, INT, BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Note 3 and 8)

 

 

 

PARAMETER

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

td(RS)

CLKOUT1 low to reset state entered

 

 

22²

ns

td(IACK)

CLKOUT1 to

 

valid

± 6

0

12

ns

IACK

td(XF)

XF valid before falling edge of

 

 

Q ± 15

 

 

ns

STRB

 

 

 

NOTES: 3. Q = 1/4tc(C).

8.RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.

timing requirements over recommended operating conditions (see Note 3 and 8)

 

 

 

 

 

 

 

 

 

 

MIN

NOM MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

tsu(IN)

 

 

 

 

 

 

 

 

 

32

 

ns

 

 

INT/BIO/RS setup before CLKOUT1 high

 

th(IN)

 

 

 

 

 

 

 

 

 

0

 

ns

 

 

INT/BIO/RS hold after CLKOUT1 high

 

t

 

 

 

 

 

 

 

 

 

 

8²

ns

 

INT/BIO fall time

 

f(IN)

 

 

 

 

 

 

 

 

 

 

 

 

tw(IN)

 

 

 

 

 

 

 

 

 

tc(C)

 

ns

 

 

INT/BIO low pulse duration

 

tw(RS)

 

 

 

low pulse duration

3tc(C)

 

ns

 

RS

 

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C).

8.RS, INT, and BIO are asynchronous inputs and can occur at any time during a clock cycle. However, if the specified setup time is met, the exact sequence shown in the timing diagrams will occur.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

 

 

 

 

 

 

PARAMETER

MIN

TYP MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

td(C1L-AL)

 

 

 

low after CLKOUT1 low

0

10

ns

HOLDA

 

tdis(AL-A)

 

 

 

low to address three-state

 

0²

ns

HOLDA

 

tdis(C1L-A)

Address three-state after CLKOUT1 low

 

 

mode, see Note 9)

 

20²

ns

(HOLD

 

td(HH-AH)

 

high to

 

high

 

25

ns

HOLD

HOLDA

 

ten(A-C1L)

Address driven before CLKOUT1 low

 

 

mode, see Note 9)

 

8²

ns

(HOLD

 

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C).

9.A15-A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as ªaddress.º

timing requirements over recommended operating conditions (see Note 3)

 

 

 

MIN NOM

MAX

UNIT

 

 

 

 

td(C2H-H)

 

valid after CLKOUT2 high

 

Q ± 24

ns

HOLD

 

NOTE 3: Q = 1/4tc(C).

ADVANCE INFORMATION

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsPGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Wait States for Communication to Slower Off-Chip Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Memory SpaceType ArchitectureTMS320 Second-Generation Device Overview PackageSECOND-GENERATION Devices Functional block diagram TMS320C2xMemory control TimerScaling shifter 16 ⋅ 16-bit parallel multiplierMemory Maps TMS320 SECOND-GENERATION DevicesExternal interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary ZAC SUBT²XOR XORK²LTP ² ApacLPH ² LTAData Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Documentation support Specification overviewMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing IPP1 Eprom ProgrammingSee Notes 14 VPPCLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high MIN TYP MAX Contrast Summary of Electrical SpecificationsClock characteristics and timing ParameterSerial port timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Hold timingClock timing Timing DiagramsBR, PS, D S Memory read timingReady CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Execute Hold timing part aHold HoldaCLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellEPT VPP Pin Nomenclature TMS320E25VCC EPTErasure TMS320E25 Programming Mode LevelsSignal Program Read Output Name ² PIN Verify Inhibit DisableProgram verify Fast Programming FlowchartRead Output disableROM protection and verification VSS Clkin EPT VPP TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VIH VIL PGM VPP VCCRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice
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