Texas Instruments TMS320 specifications One wait-state memory access timing, Msc

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ADVANCE INFORMATION

TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

one wait-state memory access timing

CLKOUT1

CLKOUT2

STRB
A15-A0, BR,	th(C2H-R)
A15-A0, BR,
PS, DS, R/W or	Valid
IS
th(C2H-R)	td(C2H-R)
td(C2H-R)
READY
td(M-R)	th(M-R)
th(M-R)	td(M-R)
D15-D0
(For Read	Data In
Operation)
D15-D0
(For Write	Data Out
Operation)
td(MSC)
td(MSC)
MSC

44	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Key Features TMS32020 Bit-Reversed Indexed-Addressing Mode forMemory Space Wait States for Communication to Slower Off-ChipArchitecture TMS320 Second-Generation Device OverviewPackage TypeFunctional block diagram TMS320C2x SECOND-GENERATION DevicesTimer Scaling shifter16 ⋅ 16-bit parallel multiplier Memory controlTMS320 SECOND-GENERATION Devices Memory MapsMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary SUBT² XORXORK² ZACApac LPH ²LTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation supportParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing Eprom Programming See Notes 14VPP IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Contrast Summary of Electrical Specifications Clock characteristics and timingParameter MIN TYP MAXMemory and peripheral interface timing RS, INT, BIO, and XF timingHold timing Serial port timingTiming Diagrams Clock timingReady Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Hold timing part a HoldHolda ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsParameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationPin Nomenclature TMS320E25 VCCEPT EPT VPPTMS320E25 Programming Mode Levels SignalProgram Read Output Name ² PIN Verify Inhibit Disable ErasureFast Programming Flowchart Program verifyROM protection and verification Output disableRead TMS320E25 Protect and Verify Eprom Mode Levels Eprom protectVIH VIL PGM VPP VCC VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice