Texas Instruments specifications Pin Nomenclature TMS320E25, Vcc, Ept Vpp

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TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

Figure 9 shows the wiring conversion to program the TMS320E25 using the 28-pin pinout of the TMS27C64. The pin nomenclature table provides a description of the TMS27C64 pins. The code to be programmed into the device should be serial mode. The TMS320E25 uses 13 address lines to address the 4K-word memory in byte format.

TMS27C64

D7

VCC

28

D6

27

PGM

D5

EPT

26

D4

A8

25

D3

A9

24

D2

A11

23

D1

22

G

D0

A10

21

20

E

Q8

19

Q7

18

E

Q6

17

Q5

16

EPT

Q4

15

VPP

A0

9	8																						RS



			7		6		5		4		3		2		1		68		67		66			65			64		63		62		61
10																							60
11																							59
11																							59
12																							58
12																							58
13																							57
13																							57
14																							56
14																							56
15																							55
15																							55
16																							54
16																							54
17												TMS320E25											53
17																							53
18																							52
18												68-Pin (FZ)											52
19																							51
19																							51
20																							50
20																							50
21																							49
21																							49
22																							48
22																							48
23																							47
23																							47
																							46
24																							46
																							45
25																							45
																							44
26																							44

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

CLKIN

INFORMATION

SS	A1	A2	A3	A4	A5	A6	A7	CC
V								V
			8

TMS27C64	PP	A12	A7	A6	A5	A4	A3
	V
	1	2	3	4	5	6	7

A8 K	A10	A11	A12	PGM		G
A9
3.9

A2	A1	A0	Q1	Q2	Q3	GND
8	9	10	11	12	13	14

ADVANCE

		Pin Nomenclature (TMS320E25)

SIGNALS	I/O		DEFINITION

A12 (MSB) - A0 (LSB)	I		On-chip EPROM programming address lines
CLIN	I		Clock oscillator input
E	I		EPROM chip select
EPT	I		EPROM test mode select
G	I		EPROM read/verify select
GND	I		Ground
PGM	I		EPROM write/program select
Q8 (MSB) - Q1 (LSB)	I/O		Data lines for byte-wide programming of on-chip 8K bytes of EPROM
RS	I		Reset for initializing the device
VCC	I		5-V power supply
VPP	I		12.5-V power supply

Figure 9. TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

59

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Wait States for Communication to Slower Off-Chip Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Memory SpaceType ArchitectureTMS320 Second-Generation Device Overview PackageSECOND-GENERATION Devices Functional block diagram TMS320C2xMemory control TimerScaling shifter 16 ⋅ 16-bit parallel multiplierMemory Maps TMS320 SECOND-GENERATION DevicesMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary ZAC SUBT²XOR XORK²LTP ² ApacLPH ² LTAData Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Documentation support Specification overviewParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing IPP1 Eprom ProgrammingSee Notes 14 VPPMP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high MIN TYP MAX Contrast Summary of Electrical SpecificationsClock characteristics and timing ParameterSerial port timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Hold timingClock timing Timing DiagramsReady Memory read timingBR, PS, D S CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Execute Hold timing part aHold HoldaHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellEPT VPP Pin Nomenclature TMS320E25VCC EPTErasure TMS320E25 Programming Mode LevelsSignal Program Read Output Name ² PIN Verify Inhibit DisableProgram verify Fast Programming FlowchartROM protection and verification Output disableRead VSS Clkin EPT VPP TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VIH VIL PGM VPP VCCRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice