Texas Instruments Programming the TMS320E25 Eprom cell, Fast programming and verification

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TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

programming the TMS320E25 EPROM cell

The TMS320E25 includes a 4K ⋅ 16-bit EPROM, implemented from an industry-standard EPROM cell, to perform prototyping and early field testing and to achieve low-volume production. When used with a 4K-word masked-ROM TMS320C25, the TMS320E25 yields a high-volume, low-cost production as a result of more migration paths for data. An EPROM adapter socket (part # TMDX3270120), shown in Figure 8, is available to provide 68-pin to 28-pin conversion for programming the TMS320E25.

ADVANCE
INFORMATION	Figure 8. EPROM Adapter Socket
	Figure 8. EPROM Adapter Socket

Key features of the EPROM cell include standard programming and verification. For security against copyright violations, the EPROM cell features an internal protection mechanism to prevent proprietary code from being read. The protection feature can be used to protect reading the EPROM contents. This section describes erasure, fast programming and verification, and EPROM protection and verification.

fast programming and verification

The TMS320E25 EPROM cell is programmed using the same family and device codes as the TMS27C64 8K ⋅ 8-bit EPROM. The TMS27C64 EPROM series are ultraviolet-light erasable, electrically programmable read-only memories, fabricated using HVCMOS technology. The TMS27C64 is pin-compatible with existing 28-pin ROMs and EPROMs. The TMS320E25, like the TMS27C64, operates from a single 5-V supply in the read mode; however, a 12.5-V supply is needed for programming. All programming signals are TTL level. For programming outside the system, existing EPROM programmers can be used. Locations may be programmed singly, in blocks, or at random. When programmed in blocks, the data is loaded into the EPROM cell one byte at a time, the high byte first and the low byte second.

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionPGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-ChipPackage ArchitectureTMS320 Second-Generation Device Overview TypeFunctional block diagram TMS320C2x SECOND-GENERATION Devices16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory controlTMS320 SECOND-GENERATION Devices Memory MapsExternal interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZACLTA ApacLPH ² LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Specification overview Documentation supportMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitHold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAXHold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timingTiming Diagrams Clock timingBR, PS, D S Memory read timingReady Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Holda Hold timing part aHold ExecuteCLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsPin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationEPT Pin Nomenclature TMS320E25VCC EPT VPPProgram Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal ErasureFast Programming Flowchart Program verifyRead Output disableROM protection and verification VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice