Texas Instruments TMS320 specifications VOH Min

Page 30

TMS320C25, TMS320E25

ADVANCE INFORMATION

	SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990
	2.0	V	VIH (Min)	2.4 V	VOH (Min)
	1.88	V	VIH (Min)	2.2 V	VOH (Min)
	1.88	V		2.2 V
	0.92	V	VIL (Max)	0.8 V	VOL (Max)
	0.80	V	VIL (Max)	0.6 V	VOL (Max)
	0.80	V		0.6 V
		0			0

(a) Input

(b) Output

Figure 5. Voltage Reference Levels

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER

MIN

TYP

MAX

UNIT

td(C1-S)

from CLKOUT1 (if

is present)

Q ± 6

Q

Q + 6

ns

STRB

STRB

td(C2-S)

CLKOUT2 to

(if

is present)

± 6

0

6

ns

STRB

STRB

tsu(A)

Address setup time before

low (see Note 5)

Q ± 12

ns

STRB

th(A)

Address hold time after

high (see Note 5)

Q ± 8

ns

STRB

tw(SL)

low pulse duration (no wait states, see Note 6)

2Q ± 5

2Q + 5

ns

STRB

tw(SH)

high pulse duration (between consecutive cycles, see Note 6)

2Q ± 5

2Q + 5

ns

STRB

tsu(D)W

Data write setup time before

high (no wait states)

2Q ± 20

ns

STRB

th(D)W

Data write hold time from

high

Q ± 10

Q

ns

STRB

ten(D)

Data bus starts being driven after

low (write cycle)

0²

ns

STRB

tdis(D)

Data bus three-state after

high (write cycle)

Q

Q + 15²

ns

STRB

td(MSC)

valid from CLKOUT1

± 12

0

12

ns

MSC

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4tc(C).

5.A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ªaddressº.

6.Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN

NOM MAX

UNIT

ta(A)

Read data access time from address time (read cycle, see Notes 5 and 7)

3Q ± 35

ns

tsu(D)R

Data read setup time before

high

23

ns

STRB

th(D)R

Data read hold time from

high

0

ns

STRB

td(SL-R)

READY valid after

low (no wait states)

Q ± 20

ns

STRB

td(C2H-R)

READY valid after CLKOUT2 high

Q ± 20

ns

th(SL-R)

READY hold time after

low (no wait states)

Q + 3

ns

STRB

th(C2H-R)

READY hold after CLKOUT2 high

Q + 3

ns

td(M-R)

READY valid after

valid

2Q ± 25

ns

MSC

th(M-R)

READY hold time after

valid

0

ns

MSC

NOTES: 3.

Q = 1/4tc(C).

5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as ªaddressº.

7. Read data access time is defines as ta(A) = tsu(A) + tw(SL) ± tsu(D)R.

30	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionSignals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-ChipPackage ArchitectureTMS320 Second-Generation Device Overview TypeFunctional block diagram TMS320C2x SECOND-GENERATION Devices16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory controlTMS320 SECOND-GENERATION Devices Memory MapsInterrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZACLTA ApacLPH ² LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Specification overview Documentation supportRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitRS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAXHold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timingTiming Diagrams Clock timingMemory read timing BR, PS, D SReady Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Holda Hold timing part aHold ExecuteHold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsMechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationEPT Pin Nomenclature TMS320E25VCC EPT VPPProgram Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal ErasureFast Programming Flowchart Program verifyOutput disable ReadROM protection and verification VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice