Texas Instruments TMS320 specifications Program verify, Fast Programming Flowchart

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TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

program verify

Programmed bits may be verified with VPP = 12.5 V when G = VIL, E = VIL, and PGM = VIH. Figure 11 shows the timing for the program and verify operation.

Start

Address = First

Location

VCC = 6 ± 0.25 V

VPP = 12.5 V ± 0.25

V

		X = 0
		Program One
		1-ms Pulse
		Increment X
	No
Yes		Fail
	X = 25?	Verify
	X = 25?	One
		One
		Byte
		Pass
		Program One
	Device	Pulse of
	Device	3X-ms Duration
	Failed	3X-ms Duration
	Failed

No

LastIncrement

Address?Address

Yes

VCC = VPP = 5 V ± 0.25 V

Fail	Compare All
	Bytes to Original
	Data
	Pass
	Device
	Passed

Figure 10. Fast Programming Flowchart

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsPGA and PLCC/CER-QUAD PIN Assignments Signals DefinitionFunction PIN Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-ChipTMS320 Second-Generation Device Overview ArchitecturePackage TypeSECOND-GENERATION Devices Functional block diagram TMS320C2xScaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory controlMemory Maps TMS320 SECOND-GENERATION DevicesExternal interface Interrupts and subroutinesMultiprocessing Instruction set Repeat featureAddressing modes Symbol Definition Instruction SymbolsInstruction set summary TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZACLPH ² ApacLTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Software Tools Part Number TMS320 Second-Generation Software and Hardware SupportHardware Tools Part Number Documentation support Specification overviewMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP§ MAX Unit Internal clock option Clock Characteristics and TimingExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Timing RS, INT, BIO, and XF TimingHold Holda Serial Port Timing MP/MC IOH INT Clkin / Clkx / ClkrTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1CLKIN, CLKX, Clkr INT0 INT2 VIHMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAXRS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timingClock timing Timing DiagramsBR, PS, D S Memory read timingReady CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Hold Hold timing part aHolda ExecuteCLKOUT1 CLKOUT2 Hold timing part BHolda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Pin GB grid array ceramic package TMS32020, TMS320C25 Mechanical DataParameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellVCC Pin Nomenclature TMS320E25EPT EPT VPPSignal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable ErasureProgram verify Fast Programming FlowchartRead Output disableROM protection and verification Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPPRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice