Texas Instruments TMS320 specifications Eprom Programming, See Notes 14, Vpp, IPP1, IPP2

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TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

EPROM PROGRAMMING

absolute maximum ratings over specified temperature range (unless otherwise noted)²

Supply voltage range, VPP³

± 0.6 V to 15 V

Input voltage range on pins 24 and 25

± 0.3 V to 15 V

² Stresses beyond those listed under ªAbsolute Maximum Ratingsº may cause permanent damage to the device. This is a stress ratingonly, and functional operation of the device at these or any other conditions beyond those indicated in the ªRecommended Operating Conditionsº section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

³All voltage values are with respect to GND.

recommended operating conditions

 

 

MIN

NOM

MAX

UNIT

 

 

 

 

 

 

VCC

Programming mode supply voltage (see Note 13)

 

6

 

V

VCC

Read mode supply voltage

4.75

5

5.25

V

VPP

Programming mode supply voltage

12

12.5

13

V

VPP

Read mode supply voltage (see Note 12)

 

VCC

 

V

NOTES: 12. VPP can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + IPP. During programming, VPP must be maintained at 12.5 V (± 0.25 V).

13.VCC must be applied before or at the same time as VPP and removed after or at the same time as VPP. This device must not be inserted into or removed from the board when VPP or VCC is applied.

electrical characteristics over specified temperature range (unless otherwise noted)

 

PARAMETER

TEST CONDITIONS

MIN TYP§

MAX

UNIT

IPP1

VPP supply current

VPP = VCC = 5.25 V

 

100

A

IPP2

VPP supply current (during program pulse)

VPP = 13 V

30

50

mA

§ All typical values for ICC are at VCC = 5 V, TA = 25°C.

recommended timing requirements for programming, TA = 25°C, VCC = 6 V, VPP = 12.5 V

(see Notes 14 and 15)

 

 

 

 

 

 

 

 

MIN

NOM

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

tw(IPGM)

Initial program pulse duration

0.95

1

1.05

ms

tw(FPGM)

Final pulse duration

2.85

 

78.75

ms

tsu(A)

Address setup time

2

 

 

s

tsu(E)

 

 

setup time

2

 

 

s

E

 

 

 

tsu(G)

 

 

setup time

2

 

 

s

G

 

 

tdis(G)

Output disable time from

 

 

 

0

 

130¶

ns

G

 

 

ten(G)

Output enable time from

 

 

 

 

 

 

150¶

ns

G

 

 

 

tsu(D)

Data setup time

2

 

 

s

tsu(VPP)

VPP setup time

2

 

 

s

tsu(VCC)

VCC setup time

2

 

 

s

th(A)

Address hold time

0

 

 

s

th(D)

Data hold time

2

 

 

s

Value derived from characterization data and not tested.

NOTES: 14. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V and VPP = 12.5 V ± 0.5 V during programming.

15. Common test conditions apply for tdis(G) except during programming.

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsSignals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-ChipTMS320 Second-Generation Device Overview ArchitecturePackage TypeSECOND-GENERATION Devices Functional block diagram TMS320C2xScaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory controlMemory Maps TMS320 SECOND-GENERATION DevicesInterrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZACLPH ² ApacLTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Documentation support Specification overviewRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingRS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAXRS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timingClock timing Timing DiagramsMemory read timing BR, PS, D SReady CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Hold Hold timing part aHolda ExecuteHold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellVCC Pin Nomenclature TMS320E25EPT EPT VPPSignal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable ErasureProgram verify Fast Programming FlowchartOutput disable ReadROM protection and verification Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPPRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice