Texas Instruments TMS320 specifications TsuIN Setup before CLKOUT1 high

Page 38

TMS320C25-50

ADVANCE INFORMATION

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

RS, INT, BIO, AND XF TIMING

switching characteristics over recommended operating conditions (see Notes 3 and 16)

 

 

 

PARAMETER

MIN

TYP MAX

UNIT

 

 

 

 

 

 

 

 

 

t

CLKOUT1 low to reset state entered

 

22²

ns

d(RS)

 

 

 

 

 

 

 

 

td(IACK)

CLKOUT1 to

 

valid

± 5

7

ns

IACK

td(XF)

XF valid before falling edge of

 

 

Q ± 8

 

ns

STRB

 

 

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C)

16.RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.

timing requirements over recommended operating conditions (see Notes 3 and 16)

 

 

 

 

 

 

 

 

MIN NOM

MAX

UNIT

 

 

 

 

 

 

 

 

 

 

tsu(IN)

 

 

 

 

 

 

setup before CLKOUT1 high

25

 

ns

INT,

 

BIO,

 

RS

 

th(IN)

 

 

 

 

 

 

hold after CLKOUT1 high

0

 

ns

INT,

 

BIO,

 

RS

 

t

 

 

 

 

fall time

 

8²

ns

INT,

 

BIO

 

f(IN)

 

 

 

 

 

 

 

 

 

 

tw(IN)

 

 

 

 

low pulse duration

tc(C)

 

ns

INT,

 

BIO

 

tw(RS)

 

low pulse duration

3tc(C)

 

ns

RS

 

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C)

16.RS, INT, BIO are asynchronous inputs and can occur at any time during a clock cycle.

HOLD TIMING

switching characteristics over recommended operating conditions (see Note 3)

 

 

 

 

 

PARAMETER

MIN

TYP MAX

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

low after CLKOUT1 low

1 ²

11

ns

HOLDA

d(CIL-AL)

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

low to address high-impedance

 

0 ²

ns

HOLDA

 

dis(AL-A)

 

 

 

 

 

 

 

 

 

 

 

 

t

Address high-impedance after CLKOUT1 low

 

mode, see Note 17)

 

20 ²

ns

(HOLD

 

dis(CIL-A)

 

 

 

 

 

 

 

 

 

 

 

 

td(HH-AH)

 

high to

 

high

 

19

ns

HOLD

HOLDA

 

t

Address driven before CLKOUT1 low

 

mode, see Note 17)

 

8 ²

ns

(HOLD

 

en(A-CIL)

 

 

 

 

 

 

 

 

 

 

 

 

²Value derived from characterization data and not tested. NOTES: 3. Q = 1/4 tc(C)

17.A15-A0, PS, DS, STRB, and R/W timings are all included in timings referenced as ªaddressº.

timing requirements over recommended operating conditions (see Note 3)

 

 

 

MIN

NOM MAX

UNIT

 

 

 

 

td(C2H-H)

 

valid after CLKOUT2 high

 

Q ± 19

ns

HOLD

 

NOTE 3: Q = 1/4 tc(C)

 

 

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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Contents TMS320 SECOND-GENERATION Digital Signal Processors DescriptionFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Memory Space Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Wait States for Communication to Slower Off-ChipPackage ArchitectureTMS320 Second-Generation Device Overview TypeFunctional block diagram TMS320C2x SECOND-GENERATION Devices16 ⋅ 16-bit parallel multiplier TimerScaling shifter Memory controlTMS320 SECOND-GENERATION Devices Memory MapsMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XORK² SUBT²XOR ZACLTA ApacLPH ² LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 TMS32020 Product NotificationDevelopment support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Specification overview Documentation supportParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Memory and Peripheral Interface Timing Parameter MIN TYP MAX UnitHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit External Clock Option ClkinVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing VPP Eprom ProgrammingSee Notes 14 IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr Internal Clock Option External clock option CLKOUT1, CLKOUT2Fcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Parameter Contrast Summary of Electrical SpecificationsClock characteristics and timing MIN TYP MAXHold timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Serial port timingTiming Diagrams Clock timingReady Memory read timingBR, PS, D S Memory write timing CLKOUT1 CLKOUT2 StrbOne wait-state memory access timing MSCReset timing IackInterrupt timing TMS32020 Interrupt timing TMS320C25Serial port receive timing Serial port transmit timingBIO timing External flag timingPC = N PC = N + Holda Hold timing part aHold ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH Typical Supply Current Characteristics for TMS320C25 TMS320C25FNL Plcc reflow soldering precautionsParameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Programming the TMS320E25 Eprom cell Fast programming and verificationEPT Pin Nomenclature TMS320E25VCC EPT VPPProgram Read Output Name ² PIN Verify Inhibit Disable TMS320E25 Programming Mode LevelsSignal ErasureFast Programming Flowchart Program verifyROM protection and verification Output disableRead VIH VIL PGM VPP VCC TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VSS Clkin EPT VPPEprom RbitVIH VIL VPP VCC VCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSSTMS320 SECOND-GENERATION NIL Packaging Information Other Qualified Versions of TMS320C25Important Notice
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