Texas Instruments TMS320 specifications Timing Diagrams, Clock timing

Page 41

TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

TIMING DIAGRAMS

This section contains all the timing diagrams for the TMS320 second-generation devices. Refer to the top corner of page for the specific device.

Timing measurements are referenced to and from a low voltage of 0.8 voltage and a high voltage of 2 volts, unless otherwise noted.

clock timing

		tc(CI)
		tf(CI)
		tr(CI)
X/2CLKIN
th(S)		tw(CIH)
th(S)		tw(CIL)
tsu(S)	tsu(S)	tw(CIL)
tsu(S)	tsu(S)
SYNC
		tc(C)
td(CIH-C)		tw(CL)
		td(CIH-C)
CLKOUT1
		tw(CH)
	td(CIH-C)	tr(C)		tf(C)
STRB
td(CIH-C)		tc(C)
		tc(C)
				tw(CL)
CLKOUT2
td(C1-C2)		td(C1-C2)	tf(C)	tr(C)
	td(C1-C2)	tw(CH)
td(C1-C2)

ADVANCE INFORMATION

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

41

Image 41

Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-ChipTMS320 Second-Generation Device Overview ArchitecturePackage TypeSECOND-GENERATION Devices Functional block diagram TMS320C2xScaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory controlMemory Maps TMS320 SECOND-GENERATION DevicesMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZACLPH ² ApacLTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Documentation support Specification overviewParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAXRS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timingClock timing Timing DiagramsReady Memory read timingBR, PS, D S CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Hold Hold timing part aHolda ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellVCC Pin Nomenclature TMS320E25EPT EPT VPPSignal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable ErasureProgram verify Fast Programming FlowchartROM protection and verification Output disableRead Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPPRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice