Texas Instruments specifications TMS32020 Product Notification

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TMS32020

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

TMS32020 PRODUCT NOTIFICATION

Texas Instruments has identified an unusual set of circumstances that will cause the BIT (Test Bit) instruction on the TMS32020 to affect the contents of the accumulator; ideally, the BIT instruction should not affect the accumulator. This set of conditions is:

1.The overflow mode is set (the OVM status register bit is set to one.)

2.And, the two LSBs of the BIT instruction opcode word are zero.

a.When direct memory addressing is used, every fourth data word is affected; all other locations are not affected.

b.When indirect addressing is used, the two LSBs will be zero if a new ARP is not selected or if a new ARP is selected and that ARP is 0 or 4.

3.And, adding the contents of the accumulator with the contents of the addressed data memory location, shifted by 2 (bit code), causes an overflow of the accumulator.

If all of these conditions are met, the contents of the accumulator will be replaced by the positive or negative saturation value, depending on the polarity of the overflow.

Various methods for avoiding this phenomenon are available:

•If the TMS32020 is not in the saturation mode when the BIT instruction is executed, the device operates properly and the accumulator is not affected.

•Execute the Reset Overflow Mode (ROVM) instruction immediately prior to the BIT instruction and the Set Overflow Mode (SOVM) instruction immediately following the BIT instruction.

•If direct memory addressing is being used during the BIT instructions, reorganize memory so that the page relative locations 0, 4, 8, C, 10 . . . are not used.

•If indirect addressing is being used during the Bit instruction, select a new ARP which is not AR0 or AR4. If necessary, follow the instruction with a LARP AR0 or LARP AR4 to restore the code.

•Use the Test Bit Specified by T Register (BITT) instruction instead of the BIT instruction. The BITT instruction operates correctly and will not affect the accumulator under any circumstances.

•Replace TMS32020 with TMS320C25 for ideal pin-to-pIn and object-code compatibility. The BIT instruction on the TMS320C25 executes properly and will not affect the accumulator under any circumstances.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-ChipTMS320 Second-Generation Device Overview ArchitecturePackage TypeSECOND-GENERATION Devices Functional block diagram TMS320C2xScaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory controlMemory Maps TMS320 SECOND-GENERATION DevicesMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZACLPH ² ApacLTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Documentation support Specification overviewParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1MP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAXRS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timingClock timing Timing DiagramsReady Memory read timingBR, PS, D S CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Hold Hold timing part aHolda ExecuteHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellVCC Pin Nomenclature TMS320E25EPT EPT VPPSignal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable ErasureProgram verify Fast Programming FlowchartROM protection and verification Output disableRead Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPPRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice