Texas Instruments TMS320 specifications Serial port receive timing, Serial port transmit timing

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TMS320 SECOND-GENERATION

DEVICES

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

serial port receive timing

tc(SCK)

tr(SCK)

tw(SCK)

CLKR

th(DR)	tf(SCK)
th(FS)	tw(SCK)

FSR

tsu(FS)

tsu(DR)

DR

serial port transmit timing

	tc(SCK)
tw(SCK)		tr(SCK)
CLKX
td(CH-DX)
	tf(SCK)	tw(SCK)
th(FS)		tw(SCK)
FSX
(Input,
TXM = 0)
tsu(FS)	td(FL-DX)	td(CH-DX)
	td(FL-DX)
DX	N = 1	N = 8,16
td(CH-FS)	td(CH-FS)
td(CH-FS)
FSX
(Output,
TXM = 1)

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsFunction PIN Signals DefinitionPGA and PLCC/CER-QUAD PIN Assignments Introduction Wait States for Communication to Slower Off-Chip Key Features TMS32020Bit-Reversed Indexed-Addressing Mode for Memory SpaceType ArchitectureTMS320 Second-Generation Device Overview PackageSECOND-GENERATION Devices Functional block diagram TMS320C2xMemory control TimerScaling shifter 16 ⋅ 16-bit parallel multiplierMemory Maps TMS320 SECOND-GENERATION DevicesMultiprocessing Interrupts and subroutinesExternal interface Addressing modes Repeat featureInstruction set Instruction set summary Instruction SymbolsSymbol Definition TMS320C25 Instruction Set Summary ZAC SUBT²XOR XORK²LTP ² ApacLPH ² LTAData Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support Hardware Tools Part Number TMS320 Second-Generation Software and Hardware SupportSoftware Tools Part Number Documentation support Specification overviewParameter Test Conditions MIN TYP§ MAX Unit Recommended operating conditionsMIN NOM MAX Unit External clock option Clock Characteristics and TimingInternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingHold Holda RS, INT, BIO, and XF TimingHold Timing Serial Port Timing TMS320C25GBA INT Clkin / Clkx / ClkrMP/MC IOH Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing IPP1 Eprom ProgrammingSee Notes 14 VPPMP/MC VIL INT0 INT2 VIHCLKIN, CLKX, Clkr CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high MIN TYP MAX Contrast Summary of Electrical SpecificationsClock characteristics and timing ParameterSerial port timing Memory and peripheral interface timingRS, INT, BIO, and XF timing Hold timingClock timing Timing DiagramsReady Memory read timingBR, PS, D S CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Execute Hold timing part aHold HoldaHolda Fetch Hold timing part BCLKOUT1 CLKOUT2 Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Parameter MAX Unit Mechanical DataPin GB grid array ceramic package TMS32020, TMS320C25 Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellEPT VPP Pin Nomenclature TMS320E25VCC EPTErasure TMS320E25 Programming Mode LevelsSignal Program Read Output Name ² PIN Verify Inhibit DisableProgram verify Fast Programming FlowchartROM protection and verification Output disableRead VSS Clkin EPT VPP TMS320E25 Protect and Verify Eprom Mode LevelsEprom protect VIH VIL PGM VPP VCCRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice