Texas Instruments TMS320 specifications Jedec NO. Outline Terminals MIN MAX

Page 57

TMS320E25

SPRS010B Ð MAY 1987 Ð REVISED NOVEMBER 1990

MECHANICAL DATA

68-lead FZ CER-QUAD, ceramic leaded chip carrier package (TMS320E25 only)

This hermetically-sealed chip carrier package consists of a ceramic base, ceramic cap, and a 68-lead frame. Hermetic sealing is accomplished with glass. The FZ package is intended for both socket- or surface- mounting. Having a Sn/Pb ratio of 60/40, the tin/lead-coated leads do not require special cleaning or processing when being surface-mounted.

 

 

 

 

A

 

 

 

 

4,57 (0.180)

 

 

 

 

(see Note 2)

 

3,55 (0.140)

3,94 (0.155)

 

 

 

 

 

B

 

 

 

 

 

1,02 (0.040) ⋅ 45°

 

 

 

 

 

3,05 (0.120)

 

1,27 (0.050) Typ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Note 3)

 

A

 

 

 

 

 

 

 

 

 

C

INFORMATION

B

 

 

 

 

 

 

 

 

(At Seating

(see Note 2)

 

 

 

 

 

0,81 (0.032)

 

 

 

 

 

 

 

 

 

 

 

Plane)

 

 

 

 

 

 

 

0,66 (0.026)

 

 

 

 

 

 

 

 

 

 

 

 

 

0,51 (0.020)

(see Note 1)

 

 

 

 

0,64 (0.025)

 

 

0,36 (0.014)

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

1,016 (0.040) Min

 

 

 

 

 

 

Max

 

 

 

 

 

 

 

 

 

 

Ref

 

Thermal Resistance Characteristics

3 Places

 

 

 

 

 

3,05 (0.120)

ADVANCE

 

 

 

 

 

 

 

 

 

 

PARAMETER

 

MAX

UNIT

 

 

 

2,29 (0.090)

RθJA

Junction-to-free-air

49

°C/W

 

 

 

Seating Plane

 

thermal resistance

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Note 4)

 

RθJC

Junction-to-case

8

°C/W

 

 

 

 

 

thermal resistance

 

 

 

 

 

 

JEDEC

 

NO. OF

 

A

 

 

B

C

 

 

 

 

 

 

 

 

 

 

 

 

OUTLINE

TERMINALS

MIN

MAX

MIN

MAX

MIN

MAX

 

MO-087AA

 

28

 

12,32

12,57

10,92

11,56

10,41

10,92

 

 

(0.485)

(0.465)

(0.430)

(0.455)

(0.410)

(0.430)

 

 

 

 

 

 

MO-087AB

 

44

 

17,40

17,65

16,00

16,64

15,49

16,00

 

 

(0.685)

(0.695)

(0.630)

(0.655)

(0.610)

(0.630)

 

 

 

 

 

 

 

±±±

 

68

 

25,02

25,27

23,62

24,26

23,11

23,62

 

 

 

(0.985)

(0.995)

(0.930)

(0.955)

(0.910)

(0.930)

 

 

 

 

 

 

 

ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES

 

NOTES: 1. Glass is optional, and the diameter is dependent on device application.

2.Centerline of center pin, each side, is within 0,10 (0.004) of package centerline as determined by dimension B.

3.Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.

4.The lead contact points are within 0,15 (0.006) of being planar.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001

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Contents Description TMS320 SECOND-GENERATION Digital Signal ProcessorsSignals Definition PGA and PLCC/CER-QUAD PIN AssignmentsFunction PIN Introduction Bit-Reversed Indexed-Addressing Mode for Key Features TMS32020Memory Space Wait States for Communication to Slower Off-ChipTMS320 Second-Generation Device Overview ArchitecturePackage TypeSECOND-GENERATION Devices Functional block diagram TMS320C2xScaling shifter Timer16 ⋅ 16-bit parallel multiplier Memory controlMemory Maps TMS320 SECOND-GENERATION DevicesInterrupts and subroutines External interfaceMultiprocessing Repeat feature Instruction setAddressing modes Instruction Symbols Symbol DefinitionInstruction set summary TMS320C25 Instruction Set Summary XOR SUBT²XORK² ZACLPH ² ApacLTA LTP ²Data Memory Operations Mnemonic Description Words TMS320C25 Instruction Set Summary concluded TMS32020 Product Notification TMS32020Development support TMS320 Second-Generation Software and Hardware Support Software Tools Part NumberHardware Tools Part Number Documentation support Specification overviewRecommended operating conditions MIN NOM MAX UnitParameter Test Conditions MIN TYP§ MAX Unit Clock Characteristics and Timing Internal clock optionExternal clock option Test Load Circuit Parameter MIN TYP MAX Unit Memory and Peripheral Interface TimingRS, INT, BIO, and XF Timing Hold TimingHold Holda Serial Port Timing INT Clkin / Clkx / Clkr MP/MC IOHTMS320C25GBA Parameter Test Conditions MIN TYP MAX Unit Clkin External Clock OptionVOH Min TdC1L-AL Low after CLKOUT1 low Serial Port Timing See Notes 14 Eprom ProgrammingVPP IPP1INT0 INT2 VIH CLKIN, CLKX, ClkrMP/MC VIL CLKOUT1, CLKOUT2 Internal Clock Option External clock optionFcrystal TdC1-S From Clkout if Is present TsuIN Setup before CLKOUT1 high Clock characteristics and timing Contrast Summary of Electrical SpecificationsParameter MIN TYP MAXRS, INT, BIO, and XF timing Memory and peripheral interface timingHold timing Serial port timingClock timing Timing DiagramsMemory read timing BR, PS, D SReady CLKOUT1 CLKOUT2 Strb Memory write timingMSC One wait-state memory access timingIack Reset timingInterrupt timing TMS320C25 Interrupt timing TMS32020Serial port transmit timing Serial port receive timingExternal flag timing BIO timingPC = N PC = N + Hold Hold timing part aHolda ExecuteHold timing part B CLKOUT1 CLKOUT2Holda Fetch Fetch Execute Or is D15-D0 TdHH-AH TMS320C25FNL Plcc reflow soldering precautions Typical Supply Current Characteristics for TMS320C25Mechanical Data Pin GB grid array ceramic package TMS32020, TMS320C25Parameter MAX Unit Advance Jedec NO. Outline Terminals MIN MAX Fast programming and verification Programming the TMS320E25 Eprom cellVCC Pin Nomenclature TMS320E25EPT EPT VPPSignal TMS320E25 Programming Mode LevelsProgram Read Output Name ² PIN Verify Inhibit Disable ErasureProgram verify Fast Programming FlowchartOutput disable ReadROM protection and verification Eprom protect TMS320E25 Protect and Verify Eprom Mode LevelsVIH VIL PGM VPP VCC VSS Clkin EPT VPPRbit EpromVCC VIH VIL PGM VIH/VOH HI-Z VIL/VOL VPP EPT VSS VIH VIL VPP VCCTMS320 SECOND-GENERATION NIL Other Qualified Versions of TMS320C25 Packaging InformationImportant Notice
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