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IXP43X manual
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Contents
Main
HDG April 2007
Contents
Figures
Tables
Page
Revision History
Page
1.0 Introduction
1.1 Content Overview
1.2 Related Documentation
Tab le 1 lists the acronyms and abbreviations used in this guide.
1.3 Acronyms
Table 1. List of Acronyms and Abbreviations (Sheet 1 of 2)
1.4 Overview
Page
Document Number: 316844; Revision: 001US 13
Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors
Figure 1. Intel IXP435 Network Processor Block Diagram
64 bits
/200MHzx
16 GPIO
HSS UTOPIA 2/ MI I
1.5 Typical Applications
2.0 System Architecture
2.1 System Architecture Description
2.2 System Memory Map
Intel IXP43X Product Line of Network ProcessorsHardware Design Guidelines
HDG April 2007 16 Document Number: 316844; Revision: 001US
Intel IXP43X Product Line of Network Processors
3.0 General Hardware Design Considerations
3.1 Soft Fusible Features
3.2 DDRII/I SDRAM Interface
3.2.1 Signal Interface
Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 1 of 2)
3.2.2 DDRII/I SDRAM Initialization
Table 4. DDRII/I SDRAM Interface Pin Description (Sheet 2 of 2)
3.3 Expansion Bus
3.3.1 Signal Interface
3.3.2 Reset Configuration Straps
Table 6. Boot/Reset Strapping Configuration (Sheet 2 of 2)
3.3.3 8-Bit Device Interface
3.3.4 16-Bit Device Interface
3.3.5 Flash Interface
8-Bit Device
Byte Access
16-Bit Device
16-Bi t-W o r d A ccess
Intel I XP43X Product Line of Net work
16-Bit Device
16-Bi t- Word A ccess
Flash
Intel
Intel IXP43X Product Line of Net work Processors
3.4.1 Signal Interface
Page
3.5.1 Signal Interface MII
Table 9. MII NPE A Signal Recommendations
Table 10. MII NPE C Signal Recommendations (Sheet 1 of 2)
3.5.2 Device Connection, MII
Table 11. MAC Management Signal Recommendations - NPE A and NPE C
Table 10. MII NPE C Signal Recommendations (Sheet 2 of 2)
3.6 GPIO Interface
Intel IXP43X Product Line of Netwo rk Processors
3.6.1 Signal Interface
3.6.2 Design Notes
3.7 USB Interface
3.7.1 Signal Interface
Table 13. USB Host Signal Recommendations
Page
Intel IXP43X Product Line of Network ProcessorsHardware Design Guidelines
1
HDG April 2007 36 Document Number: 316844; Revision: 001US
Figure 8. USB RCOMP and ICOMP Pin Requirement
resisto r
Figure 9. USB Host Down Stream Interface Example
3.8 UTOPIA Level 2 Interface
3.8.1 Signal Interface
Table 14. UTOPIA Level 2/MII_A
Page
Page
Page
3.8.2 Device Connection
3.9 HSS Interface
Intel IXP43X Product Line of Network Processors
3.9.1 Signal Interface
3.9.2 Device Connection
Table 15. High-Speed, Serial Interface 0
Intel IXP43X Product Line of Network Processors
Document Number: 316844; Revision: 001US 43
3.10 SSP Interface
Figure 11. HSS Interface Example
SSP Interface
33 MHz
AFE
3.10.1 Signal Interface
3.10.2 Device Connection
3.11 PCI Interface
Intel IXP43X Product Line of Network Processors
3.11.1 Signal Interface
Table 17. PCI Controller (Sheet 1 of 2)
3.11.2 PCI Interface Block Diagram
3.11.3 PCI Option Interface
Intel IXP43X Product Line of Network Pro ces sor s
Table 18. PCI Host/Option Interface Pin Description (Sheet 2 of 3)
3.11.4 Design Notes
3.12 JTAG Interface
3.12.1 Signal Interface
3.13 Input System Clock
3.13.1 Clock Signals
3.13.2 Clock Oscillator
3.13.3 Recommendations for Crystal Selection
Intel IXP43X Product Line of Network
Page
3.14.1 Decoupling Capacitance Recommendations
3.14.2 VCC Decoupling
3.14.3 VCC33 Decoupling
3.14.4 VCCDDR Decoupling
3.14.5 Power Sequence
Page
4.0 General PCB Guide
4.1 PCB Overview
4.2 General Recommendations
4.3 Component Selection
4.4 Component Placement
4.5 Stack-Up Selection
PCB
Inexpensive Manufactured by virtually all printed-circuit-board vendors
Page
Document Number: 316844; Revision: 001US 59
Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors
Figure 17. 8-Layer Stackup
GND
Figure 18. 6-Layer Stackup
POWER
GND POWER
5.0 General Layout and Routing Guide
5.1 Overview
5.2 General Layout Guidelines
5.2.1 General Component Spacing
VIAs
Page
PBGA Package
5.2.2 Clock Signal Considerations
60 mils min
60 mils min 60 mils min
5.2.3 MII Signal Considerations
5.2.4 USB V2.0 Considerations
5.2.5 Crosstalk
5.2.6 EMI Design Considerations
5.2.7 Trace Impedance
5.2.8 Power and Ground Plane
Page
6.0 PCI Interface Design Considerations
6.1 Electrical Interface
6.2 Topology
A
BBB
6.3 Clock Distribution
6.3.1 Trace Length Limits
PCI D evi ces
Driver
6.3.2 Routing Guidelines
6.3.3 Signal Loading
7.0 DDRII / DDRI SDRAM
7.1 Introduction
Table 24. DDRII/I Signal Groups
DDR SDRAM
Intel IXP43X Product Line of Network Processors
Table 25. Supported DDRI 32-bit SDRAM Configurations
Table 26. Supported DDRII 32-bit SDRAM Configurations
Table 27. Supported DDRI 16-bit SDRAM Configurations
R1 R2
7.3 DDRII OCD Pin Requirements
Figure 27 shows the requirement for the DDRRES1 and DDRRES2 pins.
resistor
7.3.1 Signal-Timing Analysis
Figure 27. DDRII OCD Pin Requirements
T
Figure 31. DDR - Write Preamble/Postamble Duration
Table 30. DDRII-400 MHz Interface -- Signal Timings
DQS TVB6
DQS TVA6
7.3.2 Timing Relationships
Page
Table 33. Signal Package Lengths (Sheet 2 of 3)
7.3.3 Routing Guidelines
7.3.3.1 Clock Group
7.3.3.2 Data and Control Groups
Figure 32. DDRII Clock Simulation Results: CK Signals
Table 34. Clock Signal Group Routing Guidelines
DQSDQS
Figure 33. DDRII Data and Control Simulation Results: DQ and DQS signals
Table 35. DDRII Data and Control Signal Group Routing Guidelines
DQ
22 ohm
7.3.3.3 Command Groups
20ohm20ohm
Table 36. DDRII Command Signal Group Routing Guidelines