Signal Package Lengths Sheet 2 | Intel IXP43X instruction

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 33.	Signal Package Lengths (Sheet 2 of 3)

	Group	Signal Name	Length (mil)		Signal Name	Length (mil)

		D_CB0 / DDR_CB0	402.94		D_CB4 / DDR_CB4	385.50

		D_CB1 / DDR_CB1	393.93		D_CB5 / DDR_CB5	419.24

		D_CB2 / DDR_CB2	377.69		D_CB6 / DDR_CB6	398.22

		D_CB3 / DDR_CB3	378.47		D_CB7 / DDR_CB7	435.03

		D_DQ0 / DDR_DQ0	447.57		D_DQ16 /	536.32
		D_DQ0 / DDR_DQ0	447.57		DDR_DQ16	536.32
					DDR_DQ16

		D_DQ1 / DDR_DQ1	449.41		D_DQ17 /	569.24
		D_DQ1 / DDR_DQ1	449.41		DDR_DQ17	569.24
					DDR_DQ17

		D_DQ2 / DDR_DQ2	394.02		D_DQ18 /	545.35
		D_DQ2 / DDR_DQ2	394.02		DDR_DQ18	545.35
					DDR_DQ18

		D_DQ3 / DDR_DQ3	366.03		D_DQ19 /	633.70
		D_DQ3 / DDR_DQ3	366.03		DDR_DQ19	633.70
					DDR_DQ19

		D_DQ4 / DDR_DQ4	449.58		D_DQ20 /	604.01
		D_DQ4 / DDR_DQ4	449.58		DDR_DQ20	604.01
					DDR_DQ20

		D_DQ5 / DDR_DQ5	470.40		D_DQ21 /	608.22
		D_DQ5 / DDR_DQ5	470.40		DDR_DQ21	608.22
					DDR_DQ21

		D_DQ6 / DDR_DQ6	413.35		D_DQ22 /	479.46
		D_DQ6 / DDR_DQ6	413.35		DDR_DQ22	479.46
					DDR_DQ22

		D_DQ7 / DDR_DQ7	384.02		D_DQ23 /	555.12
		D_DQ7 / DDR_DQ7	384.02		DDR_DQ23	555.12
					DDR_DQ23

		D_DQ8 / DDR_DQ8	368.37		D_DQ24 /	472.85
	Data	D_DQ8 / DDR_DQ8	368.37		DDR_DQ24	472.85
					DDR_DQ24

		D_DQ9 / DDR_DQ9	399.54		D_DQ25 /	475.30
		D_DQ9 / DDR_DQ9	399.54		DDR_DQ25	475.30
					DDR_DQ25

		D_DQ10/ DDR_DQ10	374.55		D_DQ26 /	421.35
		D_DQ10/ DDR_DQ10	374.55		DDR_DQ26	421.35
					DDR_DQ26

		D_DQ11 / DDR_DQ11	398.20		D_DQ27 /	419.04
		D_DQ11 / DDR_DQ11	398.20		DDR_DQ27	419.04
					DDR_DQ27

		D_DQ12 / DDR_DQ12	396.30		D_DQ28 /	480.43
		D_DQ12 / DDR_DQ12	396.30		DDR_DQ28	480.43
					DDR_DQ28

		D_DQ13 / DDR_DQ13	408.81		D_DQ29 /	489.89
		D_DQ13 / DDR_DQ13	408.81		DDR_DQ29	489.89
					DDR_DQ29

		D_DQ14 / DDR_DQ14	371.03		D_DQ30 /	430.18
		D_DQ14 / DDR_DQ14	371.03		DDR_DQ30	430.18
					DDR_DQ30

		D_DQ15 / DDR_DQ15	388.23		D_DQ31 /	431.50
		D_DQ15 / DDR_DQ15	388.23		DDR_DQ31	431.50
					DDR_DQ31

		D_DQS0 /	468.21		D_DQS2 /	517.45
		DDR_DQS0	468.21		DDR_DQS2	517.45
		DDR_DQS0			DDR_DQS2

		D_DQS1 /	371.60		D_DQS3 /	463.84
		DDR_DQS1	371.60		DDR_DQS3	463.84
		DDR_DQS1			DDR_DQS3

		D_DM0 / DDR_DM0	410.19		D_DQS4 /	653.53
		D_DM0 / DDR_DM0	410.19		DDR_DQS4	653.53
					DDR_DQS4

		D_DM1 / DDR_DM1	482.30		D_DM3 / DDR_DM3	536.80

		D_DM2 / DDR_DM2	553.44		D_DM4 / DDR_DM4	428.52

		D_CKE0 / DDR_CKE0	385.61		D_CKE1 / DDR_CKE1	384.34
	Control
	Control	D_CS_N0 /	385.35		D_CS_N1 /	421.27
		D_CS_N0 /			D_CS_N1 /
		DDR_CS_N0			DDR_CS_N1
		DDR_CS_N0			DDR_CS_N1

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	81

Image 81

Intel IXP43X manual Signal Package Lengths Sheet 2

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors Intel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content Overview Acronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term Explanation List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol Description USB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface Ethernet DDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface Signal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio Interface Gpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 Utpopfci Utpipfci ClavUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40 Device Connection HSS Interface HSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan Pciclkin PCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field Signal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling § § PCB Overview Component PlacementGeneral Recommendations Component Selection Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations MII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Group Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea DDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement Banks DDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer Stackup Signal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §