Ddrii Command Signal Group Routing Guidelines | Intel IXP43X

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 35. DDRII Data and Control Signal Group Routing Guidelines

Parameter	Definition

Minimum Spacing to Other DDR Signals	20.0 mils

Minimum Spacing to non-DDR Signals	25.0 mils

Maximum Via Count	5 per trace

Total Trace Length	1000 mils to 2000 mils

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zo.

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zdiff.

7.3.3.3Command Groups

The command signal groups include all signals D_MA[13:0]/DDR_MA[13:0],

D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS, D_CAS/DDR_CAS and D_WE/DDR_WE. The groups should be routed on internal layers, except for pin escapes. It is recommended that pin escape vias be located directly adjacent to the ball pads on all signals. Surface layer routing should be minimized. The following table provides routing guidelines for signals within these groups.

Figure 34. DDRII Command Simulation Results: ADDRESS signals

20ohm

Table 36. DDRII Command Signal Group Routing Guidelines

	Parameter	Definition

	Signal Group Members	D_MA[13:0]/DDR_MA[13:0], D_BA[1:0]/DDR_BA[1:0], D_RAS/DDR_RAS,
	Signal Group Members	D_CAS/DDR_CAS and D_WE/DDR_WE.
		D_CAS/DDR_CAS and D_WE/DDR_WE.

	Topology	Point to Point (1 Driver, 10Receivers)

	Single Ended Trace Impedance (Zo)	50 Ω

Notes:

1.Nominal trace width is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zo.

2.Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zdiff.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	85

Image 85

Intel IXP43X manual Ddrii Command Signal Group Routing Guidelines, Signal Group Members

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors HDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Chapter Name Description Content Overview Acronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term Explanation List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol Description USB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface Ethernet DDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Expansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface MII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII MII Interface Example Gpio Interface USB Interface Gpio Signal RecommendationsDesign Notes Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 Utpopfci Utpipfci ClavUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40 Device Connection HSS Interface HSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan Pciclkin PCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field Signal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling § § PCB Overview Component PlacementGeneral Recommendations Component Selection Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations USB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Group Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea DDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement Banks Ddrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer Stackup Group Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §