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manual Hardware Design Guidelines, Intel IXP43X Product Line of Network Processors
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Intel IXP435 Network Processor Block Diagram
Processors Datasheet
Component Placement
Reset Configuration Straps
being disabled without asserting a system reset
Command Groups
DDRII Data and Control Simulation Results DQ and DQS signals
Setting Intel XScale Processor Operation Speed
Weight
Page 1
Image 1
Intel
®
IXP43X Product Line of Network Processors
Hardware Design Guidelines
April 2007
Document Number:
316844;
Revision:
001US
Page 2
Page 1
Image 1
Page 2
Contents
Intel IXP43X Product Line of Network Processors
Hardware Design Guidelines
April
April
Intel IXP43X Product Line of Network Processors
Introduction
Contents
Figures
DDRII Data and Control Simulation Results DQ and DQS signals
Tables
MAC Management Signal Recommendations NPE A and NPE C
Pad-to-Pad Clearance of Passive Components to a PGA or BGA
DDR Clock Timings
April
Revision History
April
Intel IXP43X Product Line of Network Processors
Document Number 316844 Revision 001US
1.0 Introduction
1.1 Content Overview
1.3 Acronyms
1.2 Related Documentation
Intel IXP43X Product Line of Network Processors Datasheet
Intel IXP400 Software Specification Update
Table 1. List of Acronyms and Abbreviations Sheet 2 of
1.4 Overview
16 GPIO General Purpose Input Output Packaging 460-pin PBGA
Figure 1. Intel IXP435 Network Processor Block Diagram
1.5 Typical Applications
2.1 System Architecture Description
2.0 System Architecture
2.2 System Memory Map
Header
JTAG
Processors
Memory Bus
3.0 General Hardware Design Considerations
3.1 Soft Fusible Features
Table 2. Signal Type Definitions
Soft Fusible Features Sheet 1 of
Soft Fusible Features Sheet 2 of
3.2 DDRII/I SDRAM Interface
DDRII/I SDRAM Interface Pin Description Sheet 1 of
3.2.1 Signal Interface
DDRII/I SDRAM Interface Pin Description Sheet 2 of
3.2.2 DDRII/I SDRAM Initialization
3.3 Expansion Bus
3.3.1 Signal Interface
Expansion Bus Signal Recommendations Sheet 1 of
Expansion Bus Signal Recommendations Sheet 2 of
3.3.2 Reset Configuration Straps
Boot/Reset Strapping Configuration Sheet 1 of
Network Processors Developer’s Manual
Boot/Reset Strapping Configuration Sheet 2 of
Setting Intel XScale Processor Operation Speed
3.3.3 8-Bit Device Interface
April
3.3.4 16-Bit Device Interface
Document Number 316844 Revision 001US
16-Bit-Word Access
Byte Access
Intel IXP43X Product
Line of Network
3.4 UART Interface
Intel Flash
16-Bit-Word Access
16-Bit Device
UART Signal Recommendations
3.4.1 Signal Interface
1 DCD
Connector Female
2 RX
3 TX
MII NPE A Signal Recommendations
3.5.1 Signal Interface MII
MII NPE C Signal Recommendations Sheet 1 of
being disabled without asserting a system reset
MII NPE C Signal Recommendations Sheet 2 of
3.5.2 Device Connection, MII
MAC Management Signal Recommendations - NPE A and NPE C
being disabled without asserting a system reset
Network Processors
3.6 GPIO Interface
10/100
Intel IXP43X
3.7 USB Interface
3.6.1 Signal Interface
3.6.2 Design Notes
GPIO Signal Recommendations
USB Host Signal Recommendations
3.7.1 Signal Interface
Figure 7. Common Mode Choke
USB RBIASN
USB RBIASP
22.6 Ω ±1 %
resistor
3.8 UTOPIA Level 2 Interface
3.8.1 Signal Interface
UTOPIA Level 2/MIIA
Pull
Type
Name
Description
Pull
Type
Name
Description
Pull
Type
Name
Description
3.8.2 Device Connection
3.9 HSS Interface
Intel IXP43X
Product Line of
3.9.2 Device Connection
3.9.1 Signal Interface
being disabled without asserting a system reset
High-Speed, Serial Interface
Figure 11. HSS Interface Example
3.10 SSP Interface
3.10.2 Device Connection
3.10.1 Signal Interface
Synchronous Serial Peripheral Port Interface
Intel IXP43X Product
3.11 PCI Interface
Line of Network
Processors
PCI Controller Sheet 1 of
3.11.1 Signal Interface
PCI Controller Sheet 2 of
3.11.2 PCI Interface Block Diagram
Network Processors
3.11.3 PCI Option Interface
Figure 13. PCI Interface
Table 18. PCI Host/Option Interface Pin Description Sheet 1 of
Type
PCI Host/Option Interface Pin Description Sheet 2 of
Option
Name
3.11.4 Design Notes
3.12 JTAG Interface
PCI Host/Option Interface Pin Description Sheet 3 of
3.13.1 Clock Signals
3.12.1 Signal Interface
3.13 Input System Clock
3.13.2 Clock Oscillator
3.13.3 Recommendations for Crystal Selection
Network
OSCIN
33 KΩ
Power Supply
3.14 Power
Processors Datasheet
Processors Datasheet
3.14.6 Reset Timing
3.14.5 Power Sequence
3.14.1 Decoupling Capacitance Recommendations
3.14.2 VCC Decoupling
The IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page
4.0 General PCB Guide
4.4 Component Placement
4.1 PCB Overview
4.2 General Recommendations
Inexpensive
4.5 Stack-Up Selection
Manufactured by virtually all printed-circuit-board vendors
Figure 16. Component Placement on a PCB
Lack of power/ground planes, resulting in unacceptable crosstalk
Poor routing density Uncontrolled signal trace impedance
Controlled-impedance traces Low-impedance power distribution
Higher cost More weight Manufactured by fewer vendors
Figure 18. 6-Layer Stackup
Figure 17. 8-Layer Stackup
5.1 Overview
5.0 General Layout and Routing Guide
5.2 General Layout Guidelines
5.2.1 General Component Spacing
VIAs
Figure 19. Signal Changing Reference Planes
Figure 21. Poor Design Practice for VIA Placement
Figure 20. Good Design Practice for VIA Hole Placement
25 mils min 25 mils min 25 mils min
Flush Via min Potential Bridge min
PBGA Package
5.2.2 Clock Signal Considerations
Figure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA
5.2.4 USB V2.0 Considerations
5.2.3 MII Signal Considerations
5.2.5 Crosstalk
5.2.6 EMI Design Considerations
5.2.8 Power and Ground Plane
5.2.7 Trace Impedance
Use at least one decoupling capacitor per power pin and place it as close as possible to the pin
6.1 Electrical Interface
6.0 PCI Interface Design Considerations
6.2 Topology
PCI Slot
6.3 Clock Distribution
PCI Slot
PCI Slot
PCI Devices
6.3.1 Trace Length Limits
Clock
Driver
6.3.2 Routing Guidelines
6.3.3 Signal Loading
This manual does not repeat all the guidelines that are already stated in the
7.1 Introduction
7.0 DDRII / DDRI SDRAM
Signal Name
DDRII/I Signal Groups
Group
Description
Processors
DDR SDRAM
Product Line of Network
IXP43X
Supported DDRII 32-bit SDRAM Configurations
Supported DDRI 32-bit SDRAM Configurations
Supported DDRI 16-bit SDRAM Configurations
R1 =387 Ω ±1 % resistor
DDRI
R 1 = 285 Ω ±1 % resistor
DDRIMPCRES
7.3.1 Signal-Timing Analysis
7.3 DDRII OCD Pin Requirements
Figure 27. DDRII OCD Pin Requirements
Figure 28. DDR Clock Timing Waveform
Figure 30. DDR SDRAM Read Timings
Figure 29. DDR SDRAM Write Timings
ADDR/CTRL
CS10# CK DQS DQS # DQ
Figure 31. DDR - Write Preamble/Postamble Duration
DDRII-400 MHz Interface -- Signal Timings
See Figure 29, “DDR SDRAM Write Timings” on page
DDR II/I SDRAM Interface -- Signal Timings
7.3.2 Timing Relationships
7.3.1.0.1 Printed Circuit Board Layer Stackup
Table 31 on page
Signal Package Lengths Sheet 1 of
Table 32 on page Table 33 on page
Figure 30 on page Table 32 on page
Signal Name
Signal Package Lengths Sheet 2 of
Signal Name
Group
7.3.3.1 Clock Group
7.3.3 Routing Guidelines
Signal Package Lengths Sheet 3 of
Figure 32. DDRII Clock Simulation Results CK Signals
7.3.3.2 Data and Control Groups
Clock Signal Group Routing Guidelines
Table 35. DDRII Data and Control Signal Group Routing Guidelines
22 ohm
20ohm
7.3.3.3 Command Groups
Table 35. DDRII Data and Control Signal Group Routing Guidelines
Figure 34. DDRII Command Simulation Results ADDRESS signals
Table 36. DDRII Command Signal Group Routing Guidelines
