Common Mode Choke | Intel IXP43X manual

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

2.If a 1.5-KΩ,pull-up resistor is connected to USB_P_NEG line, the USB port is identified as Low-speed mode.

To maintain signal integrity and minimize end-users termination mismatch, the IXP43X network processors require external series termination resistors. The value of the terminating resistors is based on the operational speed and length of the transmission line.

Refer to following termination guidelines for High-speed:

1.High-speed USB designs require parallel termination at both the transmitter and receiver. For host controller designs that use external termination resistors, place the termination resistors as close as possible to the host controller signal pins.

Recommend less than 200 mils if possible. Follow the manufacturer’s recommendation for the termination value needed to obtain the required 45 ohm to ground parallel HS termination.

2.For downstream ports, a 15 kΩ pull down resistor on the connector side of the termination is required for device connection detection purposes. Note that this pull down might be integrated into the host controller silicon. Follow the manufacturer’s recommendation for the specific part used.

3.A common mode (CM) choke should be used to terminate the high speed USB bus if they should pass EMI testing. Place the CM choke as close as possible to the connector as shown in Figure 8 on page 36. Common mode chokes can provide required noise attenuation. Design can include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing.

Note: Common mode chokes degrade signal quality, thus they should only be used if EMI is a known problem.

Figure 7. Common Mode Choke

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	35

Image 35

Intel IXP43X manual Common Mode Choke

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors April Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Chapter Name Description Content Overview Term Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1 List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1 Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram Interface Name Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Type DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface MII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C MII Interface Example Gpio Interface Design Notes Gpio Signal RecommendationsUSB Interface Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40 ETHARXDATA30 Etharxclk ClavUtpipfci Utpipsoc UTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7 Device Connection HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 Pciintan Type Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Recommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations § § Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations Crosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Dcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / Ddrrasn DDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram Configurations Technology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select Total DDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Printed Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing Relationships Timing Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §