USB Interface, Design Notes | Intel IXP43X specs

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

3.6.1Signal Interface

Table 12.		GPIO Signal Recommendations

		Type	Pull
	Name	Type	Up/	Recommendations
	Name	Field	Up/	Recommendations
		Field	Down
			Down

				General Purpose Input/Output.
				If used as an input interrupt (only GPIO [12:0]), should be pull-up or pull-down, depending
				on the level of activation. For example:
	GPIO[13:0]	IO	Yes	Active high, use a 10-KΩpull-down resistor.
				Active low, use a 10-KΩpull-up resistor.
				Should be pulled high through a 10-KΩresistor when not used.
				Note: Alternate function for GPIO[1] - External USB 48 MHz Bypass Clock

				General Purpose Input/Output.
	GPIO[14]	IO	Yes	Same recommendations as GPIO[13:0]. An additional feature includes Clock generation, max
				clock out 33.33 MHz., set as input by default.

				General Purpose Input/Output.
	GPIO[15]	IO	Yes	Same recommendations as GPIO[13:0]. An additional feature includes Clock generation, max
				clock out 33.33 MHz., set as output by default.

3.6.2Design Notes

The drive strength for GPIO[15:14] is limited to 8 mA, while GPIO [13:0] can output up to 16 mA. When used for driving high current devices such as LEDs or relays, make sure to place current-limiting resistor; else there could be permanent damage to the driver of the IXP43X network processors.

It is recommended that a 10-KΩpull-up resistor be used when a GPIO port is configured as an input and not being used.

3.7USB Interface

There are two USBV2.0 Host Controllers in the IXP43X network processors. It supports Low-Speed, 1.5 Mbps, Full-Speed, 12 Mbps, High-Speed, 480 Mbps rate and interface is EHCI compliant.

Supported features are:

•Host function

•Low-speed interface

•Full-speed interface

•High-speed interface

•EHCI register interface

•UTMI+ Level 2 Compliant

The following is a partial list of features that are not supported:

•Device function

•OTG function

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	33

Image 33

Intel IXP43X manual USB Interface, Design Notes, Gpio Signal Recommendations

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors Intel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Chapter Name Description Content Overview Acronyms Related DocumentationList of Acronyms and Abbreviations Sheet 1 Term Explanation List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Signal Type Definitions Soft Fusible FeaturesSoft Fusible Features Sheet 1 Symbol Description USB Host Each USB can be Enable separately Soft Fusible Features Sheet 2DDRII/I Sdram Interface Ethernet DDRII/I Sdram Interface Pin Description Sheet 1 Signal InterfaceType Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 2 Reset Configuration StrapsBoot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface Signal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII MII Interface Example Gpio Interface Gpio Signal Recommendations USB InterfaceDesign Notes Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA75 UTPOPDATA4UTPOPADDR40 Utpopfci Utpipfci ClavUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA6 UTPIPDATA5UTPIPDATA7 UTPIPADDR40 Device Connection HSS Interface HSSTXDATA0 High-Speed, Serial InterfaceHSSTXCLK0 HSSRXDATA0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 PCI Controller Sheet 2 PCI Interface Block DiagramPciintan Pciclkin PCI Option Interface Connect signal to same pin between PCI Parity Two devicesPCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field Signal PCIREQN0 to one PCIREQN30 inputs to the Host On the Option device, these signals are notPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Reset Timing Power SequenceDecoupling Capacitance Recommendations VCC Decoupling § § PCB Overview Component PlacementGeneral Recommendations Component Selection Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations MII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Topology Electrical Interface@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Group Signal Name Description DDRII/I Signal GroupsDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddrii 32-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea DDRII/DDRI Rcomp and Slew Resistances Pin Requirements Supported Ddrii 16-bit Sdram ConfigurationsAddress Size Leaf Select Total Technology Arrangement Banks DDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum Units DDR II/I Sdram Interface -- Signal TimingsTiming Relationships Printed Circuit Board Layer Stackup Signal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §