Signal Interface MII | Intel IXP43X manual

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

3.5.1Signal Interface MII

Table 9.			MII NPE A Signal Recommendations

				Type	Pull
		Name		Type	Up/	Recommendations
		Name		Field	Up/	Recommendations
				Field	Down
					Down

						Transmit Clock.
	ETHA_TXCLK			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
						interface/signal should be pulled high with a 10-KΩresistor.

	ETHA_TXDATA[3:0]			O	No	Transmit Data.

	ETHA_TXEN			O	No	Transmit Enable.

						Receive Clock.
	ETHA_RXCLK			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
						interface/signal should be pulled high with a 10-KΩresistor.

						Receive Data.
	ETHA_RXDATA[3:0]			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
						interface/signal should be pulled high with a 10-KΩresistor.

						Receive Data Valid.
	ETHA_RXDV			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
						interface/signal should be pulled high with a 10-KΩresistor.

						Collision Detect.
	ETHA_COL			I	Yes	If operating in a full duplex mode and there is no requirement to use the Collision
						Detect signal, then the pin must be pulled low with a 10-KΩresistor.

						Carrier Sense.
	ETHA_CRS			I	Yes	When this interface/signal is enabled and is not being used in a system design, the
						interface/signal should be pulled high with a 10-KΩresistor.

	Notes:
	1.	Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after
		being disabled without asserting a system reset.
	2.	Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left
		unconnected.
	3.	Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in Note 1 — only require
		pull-ups or pull-downs in the clock-input signals.

Table 10.		MII NPE C Signal Recommendations (Sheet 1 of 2)

			Type	Pull
	Name		Type	Up/	Recommendations
	Name		Field	Up/	Recommendations
			Field	Down
				Down

					Externally supplied transmit clock.
					• 25 MHz for 100 Mbps operation
	ETHC_txclk		I	Yes	• 2.5 MHz for 10 Mbps
	ETHC_txclk		I	Yes	This MAC contains hardware hashing capabilities that are local to the interface.

					When this interface/signal is enabled and is not being used in a system design, the
					interface/signal should be pulled high with a 10-KΩresistor.

	ETHC_txdATA[3:0]		O	No	Transmit data bus to PHY, asserted synchronously with respect to ETHC_TXCLK. This
	ETHC_txdATA[3:0]		O	No	MAC contains hardware hashing capabilities that are local to the interface.


					Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
	ETHC_txen		O	Yes	synchronously, with respect to ETHC_TXCLK, at the first nibble of the preamble, and
	ETHC_txen		O	Yes	remains asserted until all the nibbles of a frame are presented. This MAC contains

					hardware hashing capabilities that are local to the interface.

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
30	Document Number: 316844; Revision: 001US

Image 30

Intel IXP43X manual Signal Interface MII, MII NPE a Signal Recommendations, MII NPE C Signal Recommendations Sheet 1

Contents

Intel IXP43X Product Line of Network Processors Hardware Design Guidelines Intel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Content Overview Chapter Name Description List of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term Explanation Overview List of Acronyms and Abbreviations Sheet 2 HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory Map Intel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol Description DDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately Ethernet Type Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2 Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz 4 16-Bit Device Interface Flash Interface 16-Bit Device Interface Uart Interface Flash Interface Example Uart Signal Recommendations MII Interface Uart Interface Example Signal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII Gpio Interface MII Interface Example Gpio Signal Recommendations USB InterfaceDesign Notes USB Host Signal Recommendations Name Type Pull Description Field Down Common Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPADDR40 UTPOPDATA4UTPOPDATA75 Utpopfci Utpipsoc ClavUtpipfci ETHARXDATA30 Etharxclk UTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40 HSS Interface Device Connection HSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface Example PCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 Pciclkin PCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection Field PCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description Field Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Input System Clock Clock SignalsClock Signals Clock Oscillator Recommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling § § General Recommendations Component PlacementPCB Overview Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA MII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Ddrii / Ddri Sdram Introduction Drasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / Ddrcasn DDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Sizea Address Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement Banks DDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units Timing Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer Stackup Signal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock Group Data and Control Groups Parameter Definition Ddrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Command Signal Group Routing Guidelines Signal Group Members § §