DDRII/I Signal Groups, Group Signal Name Description | Intel IXP43X

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 24.	DDRII/I Signal Groups

	Group	Signal Name	Description

		D_CK[2:0] / DDR_CK[2:0]	DDRII/I SDRAM Differential Clocks
	Clocks
	Clocks	D_CK_N[2:0] /	DDRII/I SDRAM Inverted Differential Clocks
		DDR_CK_N[2:0]	DDRII/I SDRAM Inverted Differential Clocks
		DDR_CK_N[2:0]

		D_CB[7:0] / DDR_CB[7:0]	ECC Data

		D_DQ[31:0] /	Data Bus
		DDR_DQ[31:0]	Data Bus
		DDR_DQ[31:0]

	Data	D_DQS[4:0] /	Data Strobes
	Data	DDR_DQS[4:0]	Data Strobes
		DDR_DQS[4:0]

		D_DQS_N[4:0]	Complementary Data Strobes

		D_DM[4:0] /	Data Mask
		DDR_DM[4:0]	Data Mask
		DDR_DM[4:0]

		D_CKE[1:0] /	Clock Enable - one per bank
		DDR_CKE[1:0]	Clock Enable - one per bank
	Control	DDR_CKE[1:0]

		D_CS_N[1:0] /	Chip Select - one per bank
		D_CS_N[1:0] /
		DDR_CS_N[1:0]
		DDR_CS_N[1:0]

		D_MA[13:0] /	Address Bus
		DDR_MA[13:0]	Address Bus
		DDR_MA[13:0]

		D_BA[1:0] / DDR_BA[1:0]	Bank Select
	Command
	Command	D_RAS_N / DDR_RAS_N	Row Address Select
		D_RAS_N / DDR_RAS_N	Row Address Select

		D_CAS_N / DDR_CAS_N	Column Address Select

		D_WE_N / DDR_WE_N	Write Enable

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
72	Document Number: 316844; Revision: 001US

Image 72

Intel IXP43X manual DDRII/I Signal Groups, Group Signal Name Description, Drasn / Ddrrasn, Dcasn / Ddrcasn, Dwen / Ddrwen

Contents

Intel IXP43X Product Line of Network Processors Hardware Design Guidelines Intel IXP43X Product Line of Network Processors HDGApril Contents Figures Tables Document Number 316844 Revision 001US § § Date Revision Description001 Initial release HDG Content Overview Chapter Name Description Related Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term Explanation Overview List of Acronyms and Abbreviations Sheet 2 HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory Map Intel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol Description Soft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface Ethernet Signal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2 Expansion Bus Signal Recommendations Sheet 1 Expansion BusType Pull Name Recommendations Field Down Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface Flash Interface 16-Bit Device Interface Uart Interface Flash Interface Example Uart Signal Recommendations MII Interface Uart Interface Example Signal Interface MII MII NPE a Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 MII NPE C Signal Recommendations Sheet 2 MAC Management Signal Recommendations NPE a and NPE CDevice Connection, MII Gpio Interface MII Interface Example Gpio Signal Recommendations USB InterfaceDesign Notes USB Host Signal Recommendations Name Type Pull Description Field Down Common Mode Choke Host Device Utopia Level 2 Interface Utopia Level 2/MIIAType Pull Name Description Field Down UTPOPDATA4 UTPOPDATA75UTPOPADDR40 Utpopfci Clav UtpipfciUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40 HSS Interface Device Connection High-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface Example PCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan Pciclkin Connect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field On the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Power Power SupplyNominal Name Voltage Description Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling § § Component Placement PCB OverviewGeneral Recommendations Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA MII Signal Considerations USB V2.0 ConsiderationsCrosstalk Power and Ground Plane EMI Design ConsiderationsTrace Impedance § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Clock Distribution PCI Address/Data Routing GuidelinesParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Ddrii / Ddri Sdram Introduction DDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea Supported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement Banks DDR-II Symbol Parameter Units Min Max Ddrii OCD Pin RequirementsDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units DDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer Stackup Signal Package Lengths Sheet 1 Group Signal Name Length milTiming Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock Group Data and Control Groups Parameter Definition Ddrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Command Signal Group Routing Guidelines Signal Group Members § §