Gpio Interface, MII Interface Example | Intel IXP43X specification

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 6. MII Interface Example

	Intel® IXP43X
	Product Line of
	Network Processors	10/100
		10/100
		PHY
	ETH_TXEN	TXEN
	ETH_TXCLK	TXCLK
	ETH_TXDATA[3:0]	TXDATA[3:0]
	ETH_RXDV	RXDV	Magnetics	RJ45
	ETH_RXCLK	RXCLK	Magnetics	RJ45
	ETH_RXCLK	RXCLK
	ETH_RXDATA[3:0]	RXDATA[3:0]
	ETH_COL	COL	25 MHz
	ETH_CRS	CRS
		VCC (3.3 V)
		1.5 KΩ
	ETH_MDIO	MDIO
	ETH_MDC	MDC
	MII Interface
				B4101 -004

3.6GPIO Interface

The IXP43X network processors provide 16 general-purpose input/output pins to generate and capture application-specific input and output signals. Each individual pin can be programmed as an input or output.

When programmed as an input, GPIO 0 to GPIO 12 can be configured to be an interrupt source. Interrupt sources can be configured to detect either active high, active low, rising edge, falling edge, or transitional. In addition, GPIO14 and GPIO15 can be programmed to provide a user-programmable clock out.

During reset, all pins are configured as inputs and remain in this state until configured otherwise, with the exception of GPIO15, which by default provides a clock output. The driver strength of GPIO pins is sufficient to drive external LEDs with a proper limiting resistor.

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
32	Document Number: 316844; Revision: 001US

Image 32

Intel IXP43X manual Gpio Interface, MII Interface Example

Contents

Intel IXP43X Product Line of Network Processors Hardware Design Guidelines April Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Content Overview Chapter Name Description Related Documentation AcronymsList of Acronyms and Abbreviations Sheet 1 Term Explanation Overview List of Acronyms and Abbreviations Sheet 2 HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory Map Intel IXP43X Product Soft Fusible Features Signal Type DefinitionsSoft Fusible Features Sheet 1 Symbol Description Soft Fusible Features Sheet 2 USB Host Each USB can be Enable separatelyDDRII/I Sdram Interface Ethernet Signal Interface DDRII/I Sdram Interface Pin Description Sheet 1Type Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2 Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2Boot/Reset Strapping Configuration Sheet 1 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 Setting Intel XScale Processor Operation Speed 3 8-Bit Device InterfaceIntel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed MHz 4 16-Bit Device Interface Flash Interface 16-Bit Device Interface Uart Interface Flash Interface Example Uart Signal Recommendations MII Interface Uart Interface Example MII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C Gpio Interface MII Interface Example Design Notes Gpio Signal RecommendationsUSB Interface USB Host Signal Recommendations Name Type Pull Description Field Down Common Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPDATA4 UTPOPDATA75UTPOPADDR40 Utpopfci Clav UtpipfciUtpipsoc ETHARXDATA30 Etharxclk UTPIPDATA5 UTPIPDATA6UTPIPDATA7 UTPIPADDR40 HSS Interface Device Connection High-Speed, Serial Interface HSSTXDATA0HSSTXCLK0 HSSRXDATA0 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface Example PCI Controller Sheet 1 PCI Interface Block Diagram PCI Controller Sheet 2Pciintan Pciclkin Connect signal to same pin between PCI Parity Two devices PCI Option InterfacePCI Host/Option Interface Pin Description Sheet 1 Type Option Description Name Device-Pin Connection Field On the Option device, these signals are not Signal PCIREQN0 to one PCIREQN30 inputs to the HostPCI Host/Option Interface Pin Description Sheet 2 Type Option Name Device-Pin Connection Description Field Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Clock Signals Clock SignalsInput System Clock Clock Oscillator Recommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Power Sequence Reset TimingDecoupling Capacitance Recommendations VCC Decoupling § § Component Placement PCB OverviewGeneral Recommendations Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA Crosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Electrical Interface Topology@33 MHz Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Ddrii / Ddri Sdram Introduction DDRII/I Signal Groups Group Signal Name DescriptionDrasn / Ddrrasn Dcasn / Ddrcasn DDR Sdram Supported Ddri 32-bit Sdram Configurations Supported Ddrii 32-bit Sdram ConfigurationsSupported Ddri 16-bit Sdram Configurations Sizea Supported Ddrii 16-bit Sdram Configurations DDRII/DDRI Rcomp and Slew Resistances Pin RequirementsAddress Size Leaf Select Total Technology Arrangement Banks DDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units DDR II/I Sdram Interface -- Signal Timings Symbol Parameter Minimum Nom Maximum UnitsTiming Relationships Printed Circuit Board Layer Stackup Timing Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock Group Data and Control Groups Parameter Definition Ddrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Command Signal Group Routing Guidelines Signal Group Members § §