Flash Interface, Bit Device Interface | Intel IXP43X instruction

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 3. 8/16-Bit Device Interface

EX_DATA[15:0]	EX_DATA[7:0]	DATA[7:0]
Intel® IXP43X Product		8-Bit Device
Line of Network		8-Bit Device
Processors		Byte Access
EX_ADDR[23:0]	EX_ADDR[23:0]	ADDR[23:0]
EX_CS_N	CS	CS_N
EX_RD_N	OE	OE_N
EX_WR_N	WR	WR_N
EX_DATA[15:0]	EX_DATA[15:0]	DATA[15:0]
Intel® IXP43X Product		16-Bit Device
Line of Network		16-Bit Device
Processors		16-Bit-Word Access
EX_ADDR[23:0]	EX_ADDR[23:0]	ADDR[23:0]
EX_CS_N	CS	CS_N
EX_RD_N	OE	OE_N
EX_WR_N	WR	WR_N
		B4095-004

3.3.5Flash Interface

Figure 4 illustrates how a boot ROM is connected to the expansion bus. The flash (ROM) used in the block diagram is the Intel StrataFlash® memory device TE28F256J3D — 32-Mbyte, 16-bit, flash in the 56-TSOP package. The Intel StrataFlash memory TE28F256J3D is part of the 0.18-µm, 3.3-V Intel StrataFlash memory.

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Intel® IXP43X Product Line of Network Processors
HDG	April 2007
26	Document Number: 316844; Revision: 001US

Image 26

Intel IXP43X manual Flash Interface, Bit Device Interface

Contents

Intel IXP43X Product Line of Network Processors Hardware Design Guidelines April Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Content Overview Chapter Name Description List of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term Explanation Overview List of Acronyms and Abbreviations Sheet 2 HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory Map Intel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol Description DDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately Ethernet Type Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2 Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz 4 16-Bit Device Interface Flash Interface 16-Bit Device Interface Uart Interface Flash Interface Example Uart Signal Recommendations MII Interface Uart Interface Example MII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C Gpio Interface MII Interface Example Design Notes Gpio Signal RecommendationsUSB Interface USB Host Signal Recommendations Name Type Pull Description Field Down Common Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA UTPOPADDR40 UTPOPDATA4UTPOPDATA75 Utpopfci Utpipsoc ClavUtpipfci ETHARXDATA30 Etharxclk UTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40 HSS Interface Device Connection HSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface Example PCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 Pciclkin PCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection Field PCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description Field Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Input System Clock Clock SignalsClock Signals Clock Oscillator Recommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling § § General Recommendations Component PlacementPCB Overview Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA Crosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Ddrii / Ddri Sdram Introduction Drasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / Ddrcasn DDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Sizea Address Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement Banks DDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units Timing Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer Stackup Timing Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock Group Data and Control Groups Parameter Definition Ddrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Command Signal Group Routing Guidelines Signal Group Members § §