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Intel IXP43X manual Data and Control Groups, DDRII Clock Simulation Results CK Signals

Models: IXP43X

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Figure 32. DDRII Clock Simulation Results: CK Signals

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 32. DDRII Clock Simulation Results: CK Signals

Table 34.	Clock Signal Group Routing Guidelines

		Parameter	Definition

	Signal Group Members		D_CK[2:0] and D_CK_N[2:0]

	Topology		Differential Pair Point to Point (1 Driver, 4 Receivers)

	Single Ended Trace Impedance (Zo)		50 Ω
	Series Resistor		33 Ω

	Nominal Trace Width1		Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils
	Nominal Pair Spacing (edge to edge) 2		Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils
	Minimum Pair to Pair Spacing		Any layer 20mils

	Minimum Spacing to Other DDR Signals		20.0 mils

	Minimum Spacing to non-DDR Signals		25.0 mils

	Maximum Via Count		5 per trace

	Total Trace Length		500 mils to 1000 mils

	DDR_CK to DDR_CK_N Length Matching		Match total length to +/- 10 mils between clocks

	Notes:
	1.	Nominal trace width is determined by board physical characteristics and stack-up. This value should
		be verified with the PWB manufacturer to achieve the desired Zo.
	2.	Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value
		should be verified with the PWB manufacturer to achieve the desired Zdiff.

7.3.3.2Data and Control Groups

The data and control signal group includes D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] / DDR_DQ[31:0], D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0]/DDR_DM[4:0]., D_CS[1:0]/ DDR_CS[1:0] and D_CKE[1:0]/DDR_CKE[1:0]. The groups should be routed on

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	83

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Intel IXP43X Data and Control Groups, DDRII Clock Simulation Results CK Signals, Clock Signal Group Routing Guidelines

Contents

April Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors April Intel IXP43X Product Line of Network ProcessorsIntroduction ContentsFigures Pad-to-Pad Clearance of Passive Components to a PGA or BGA TablesDDRII Data and Control Simulation Results DQ and DQS signals MAC Management Signal Recommendations NPE A and NPE CDDR Clock Timings April Revision HistoryDocument Number 316844 Revision 001US Intel IXP43X Product Line of Network ProcessorsApril 1.0 Introduction 1.1 Content OverviewIntel IXP400 Software Specification Update 1.2 Related Documentation1.3 Acronyms Intel IXP43X Product Line of Network Processors DatasheetTable 1. List of Acronyms and Abbreviations Sheet 2 of 1.4 Overview16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.2 System Memory Map 2.0 System Architecture2.1 System Architecture Description Memory Bus JTAGHeader ProcessorsSoft Fusible Features Sheet 1 of 3.1 Soft Fusible Features3.0 General Hardware Design Considerations Table 2. Signal Type DefinitionsSoft Fusible Features Sheet 2 of 3.2 DDRII/I SDRAM InterfaceDDRII/I SDRAM Interface Pin Description Sheet 1 of 3.2.1 Signal InterfaceDDRII/I SDRAM Interface Pin Description Sheet 2 of 3.2.2 DDRII/I SDRAM InitializationExpansion Bus Signal Recommendations Sheet 1 of 3.3.1 Signal Interface3.3 Expansion Bus Boot/Reset Strapping Configuration Sheet 1 of 3.3.2 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 of Network Processors Developer’s Manual Boot/Reset Strapping Configuration Sheet 2 ofSetting Intel XScale Processor Operation Speed 3.3.3 8-Bit Device InterfaceDocument Number 316844 Revision 001US 3.3.4 16-Bit Device InterfaceApril Line of Network Byte Access16-Bit-Word Access Intel IXP43X Product16-Bit Device Intel Flash3.4 UART Interface 16-Bit-Word AccessUART Signal Recommendations 3.4.1 Signal Interface3 TX Connector Female1 DCD 2 RXbeing disabled without asserting a system reset 3.5.1 Signal Interface MIIMII NPE A Signal Recommendations MII NPE C Signal Recommendations Sheet 1 ofbeing disabled without asserting a system reset 3.5.2 Device Connection, MIIMII NPE C Signal Recommendations Sheet 2 of MAC Management Signal Recommendations - NPE A and NPE CIntel IXP43X 3.6 GPIO InterfaceNetwork Processors 10/100GPIO Signal Recommendations 3.6.1 Signal Interface3.7 USB Interface 3.6.2 Design NotesUSB Host Signal Recommendations 3.7.1 Signal InterfaceFigure 7. Common Mode Choke resistor USB RBIASPUSB RBIASN 22.6 Ω ±1 %UTOPIA Level 2/MIIA 3.8.1 Signal Interface3.8 UTOPIA Level 2 Interface Description TypePull NameDescription TypePull NameDescription TypePull NameProduct Line of 3.9 HSS Interface3.8.2 Device Connection Intel IXP43XHigh-Speed, Serial Interface 3.9.1 Signal Interface3.9.2 Device Connection being disabled without asserting a system resetFigure 11. HSS Interface Example 3.10 SSP InterfaceSynchronous Serial Peripheral Port Interface 3.10.1 Signal Interface3.10.2 Device Connection Processors 3.11 PCI InterfaceIntel IXP43X Product Line of NetworkPCI Controller Sheet 1 of 3.11.1 Signal InterfacePCI Controller Sheet 2 of 3.11.2 PCI Interface Block DiagramTable 18. PCI Host/Option Interface Pin Description Sheet 1 of 3.11.3 PCI Option InterfaceNetwork Processors Figure 13. PCI InterfaceName PCI Host/Option Interface Pin Description Sheet 2 ofType OptionPCI Host/Option Interface Pin Description Sheet 3 of 3.12 JTAG Interface3.11.4 Design Notes 3.13.2 Clock Oscillator 3.12.1 Signal Interface3.13.1 Clock Signals 3.13 Input System Clock33 KΩ Network3.13.3 Recommendations for Crystal Selection OSCINProcessors Datasheet 3.14 PowerPower Supply Processors Datasheet3.14.2 VCC Decoupling 3.14.5 Power Sequence3.14.6 Reset Timing 3.14.1 Decoupling Capacitance RecommendationsThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.2 General Recommendations 4.4 Component Placement4.0 General PCB Guide 4.1 PCB OverviewFigure 16. Component Placement on a PCB 4.5 Stack-Up SelectionInexpensive Manufactured by virtually all printed-circuit-board vendorsHigher cost More weight Manufactured by fewer vendors Poor routing density Uncontrolled signal trace impedanceLack of power/ground planes, resulting in unacceptable crosstalk Controlled-impedance traces Low-impedance power distributionFigure 18. 6-Layer Stackup Figure 17. 8-Layer Stackup5.2 General Layout Guidelines 5.0 General Layout and Routing Guide5.1 Overview Figure 19. Signal Changing Reference Planes VIAs5.2.1 General Component Spacing Flush Via min Potential Bridge min Figure 20. Good Design Practice for VIA Hole PlacementFigure 21. Poor Design Practice for VIA Placement 25 mils min 25 mils min 25 mils minFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.2 Clock Signal ConsiderationsPBGA Package 5.2.5 Crosstalk 5.2.3 MII Signal Considerations5.2.4 USB V2.0 Considerations 5.2.7 Trace Impedance 5.2.8 Power and Ground Plane5.2.6 EMI Design Considerations Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.2 Topology 6.0 PCI Interface Design Considerations6.1 Electrical Interface PCI Slot 6.3 Clock DistributionPCI Slot PCI SlotDriver 6.3.1 Trace Length LimitsPCI Devices ClockThis manual does not repeat all the guidelines that are already stated in the 6.3.3 Signal Loading6.3.2 Routing Guidelines 7.1 Introduction 7.0 DDRII / DDRI SDRAMDescription DDRII/I Signal GroupsSignal Name GroupIXP43X DDR SDRAMProcessors Product Line of NetworkSupported DDRI 16-bit SDRAM Configurations Supported DDRI 32-bit SDRAM ConfigurationsSupported DDRII 32-bit SDRAM Configurations DDRIMPCRES DDRIR1 =387 Ω ±1 % resistor R 1 = 285 Ω ±1 % resistorFigure 28. DDR Clock Timing Waveform 7.3 DDRII OCD Pin Requirements7.3.1 Signal-Timing Analysis Figure 27. DDRII OCD Pin RequirementsCS10# CK DQS DQS # DQ Figure 29. DDR SDRAM Write TimingsFigure 30. DDR SDRAM Read Timings ADDR/CTRLSee Figure 29, “DDR SDRAM Write Timings” on page DDRII-400 MHz Interface -- Signal TimingsFigure 31. DDR - Write Preamble/Postamble Duration 7.3.1.0.1 Printed Circuit Board Layer Stackup 7.3.2 Timing RelationshipsDDR II/I SDRAM Interface -- Signal Timings Figure 30 on page Table 32 on page Signal Package Lengths Sheet 1 ofTable 31 on page Table 32 on page Table 33 on pageGroup Signal Package Lengths Sheet 2 ofSignal Name Signal NameSignal Package Lengths Sheet 3 of 7.3.3 Routing Guidelines7.3.3.1 Clock Group Clock Signal Group Routing Guidelines 7.3.3.2 Data and Control GroupsFigure 32. DDRII Clock Simulation Results CK Signals Table 35. DDRII Data and Control Signal Group Routing Guidelines 22 ohmFigure 34. DDRII Command Simulation Results ADDRESS signals 7.3.3.3 Command Groups20ohm Table 35. DDRII Data and Control Signal Group Routing GuidelinesTable 36. DDRII Command Signal Group Routing Guidelines