Data and Control Groups, Parameter Definition | Intel IXP43X

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 32. DDRII Clock Simulation Results: CK Signals

Table 34.	Clock Signal Group Routing Guidelines

		Parameter	Definition

	Signal Group Members		D_CK[2:0] and D_CK_N[2:0]

	Topology		Differential Pair Point to Point (1 Driver, 4 Receivers)

	Single Ended Trace Impedance (Zo)		50 Ω
	Series Resistor		33 Ω

	Nominal Trace Width1		Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils
	Nominal Pair Spacing (edge to edge) 2		Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils
	Minimum Pair to Pair Spacing		Any layer 20mils

	Minimum Spacing to Other DDR Signals		20.0 mils

	Minimum Spacing to non-DDR Signals		25.0 mils

	Maximum Via Count		5 per trace

	Total Trace Length		500 mils to 1000 mils

	DDR_CK to DDR_CK_N Length Matching		Match total length to +/- 10 mils between clocks

	Notes:
	1.	Nominal trace width is determined by board physical characteristics and stack-up. This value should
		be verified with the PWB manufacturer to achieve the desired Zo.
	2.	Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value
		should be verified with the PWB manufacturer to achieve the desired Zdiff.

7.3.3.2Data and Control Groups

The data and control signal group includes D_CB[7:0]/DDR_CB[7:0], D_DQ[31:0] / DDR_DQ[31:0], D_DQS[4:0]/DDR_DQS[4:0], D_DM[4:0]/DDR_DM[4:0]., D_CS[1:0]/ DDR_CS[1:0] and D_CKE[1:0]/DDR_CKE[1:0]. The groups should be routed on

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	83

Image 83

Intel IXP43X manual Data and Control Groups, Parameter Definition

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors April Intel IXP43X Product Line of Network ProcessorsHDG Contents Figures Tables Document Number 316844 Revision 001US 001 Initial release § §Date Revision Description HDG Chapter Name Description Content Overview Term Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1 List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1 Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram Interface Name Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Type DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Type Pull Name Recommendations Field Down Expansion Bus Signal Recommendations Sheet 1Expansion Bus Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface MII NPE C Signal Recommendations Sheet 1 Signal Interface MIIMII NPE a Signal Recommendations Device Connection, MII MII NPE C Signal Recommendations Sheet 2MAC Management Signal Recommendations NPE a and NPE C MII Interface Example Gpio Interface Design Notes Gpio Signal RecommendationsUSB Interface Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Type Pull Name Description Field Down Utopia Level 2 InterfaceUtopia Level 2/MIIA Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40 ETHARXDATA30 Etharxclk ClavUtpipfci Utpipsoc UTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7 Device Connection HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 Pciintan Type Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Recommendations for Crystal Selection Nominal Name Voltage Description PowerPower Supply VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations § § Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations Crosstalk MII Signal ConsiderationsUSB V2.0 Considerations Trace Impedance Power and Ground PlaneEMI Design Considerations § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHz Parameter Routing Guidelines Clock DistributionPCI Address/Data Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Dcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / Ddrrasn DDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram Configurations Technology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select Total DDR Clock Timings DDR-II Symbol Parameter Units Min MaxDdrii OCD Pin Requirements DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Printed Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing Relationships Timing Relationships Signal Package Lengths Sheet 1Group Signal Name Length mil Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §