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Intel IXP43X manual PCI Option Interface, Network Processors, PCI Interface

Models: IXP43X

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Figure 13. PCI Interface

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Figure 13. PCI Interface

Intel® IXP43X
Product Line of
Network Processors
				Compact PCI Bus	cPCI J1
PCI Interface	PCI Bus	Transparent PCI	Bridge
PCI Interface		Transparent PCI	Bridge		J2
					cPCI
	PCI Slots
					B 4110- 003

3.11.3PCI Option Interface

The IXP43X network processors can be used in a design as a host or as an option device. This section describes how the IXP43X network processors can be connected as an option device to obtain proper functionality. There are slight differences in the hardware interface when designing for option mode. All routing and board recommendations described in this document apply, however the design must use the device pin connections listed in Table 18.

Table 18. PCI Host/Option Interface Pin Description (Sheet 1 of 3)

		Type		Option	Description
	Name	Type	Device-Pin Connection	Type
	Name	Field	Device-Pin Connection	Type
		Field		Field
				Field

	PCI_AD[31:0]	I/O	All address/data signals must be	I/O	PCI Address/Data bus
	PCI_AD[31:0]	I/O	connected between the two devices.	I/O	PCI Address/Data bus
			connected between the two devices.

	PCI_CBE_N[3:0]	I/O	Connect signals to same pins between	I/O	PCI Command/Byte Enables
	PCI_CBE_N[3:0]	I/O	the two devices.	I/O	PCI Command/Byte Enables
			the two devices.

	PCI_PAR	I/O	Connect signal to same pin between	I/O	PCI Parity
	PCI_PAR	I/O	the two devices.	I/O	PCI Parity
			the two devices.

			Connect signal to same pin between
	PCI_FRAME_N	I/O	the two devices.	I/O	PCI Cycle Frame
			Connect a 10-KΩpull-up resistor.

			Connect signal to same pin between
	PCI_TRDY_N	I/O	the two devices.	I/O	PCI Target Ready
			Connect a 10-KΩpull-up resistor.

	Intel® IXP43X Product Line of Network Processors
	HDG				April 2007
	48				Document Number: 316844; Revision: 001US

Image 48

Intel IXP43X PCI Option Interface, Network Processors, PCI Interface, PCI Host/Option Interface Pin Description Sheet 1 of

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsApril Intel IXP43X Product Line of Network Processors AprilContents IntroductionFigures Tables DDRII Data and Control Simulation Results DQ and DQS signalsMAC Management Signal Recommendations NPE A and NPE C Pad-to-Pad Clearance of Passive Components to a PGA or BGADDR Clock Timings Revision History AprilIntel IXP43X Product Line of Network Processors AprilDocument Number 316844 Revision 001US 1.1 Content Overview 1.0 Introduction1.2 Related Documentation 1.3 AcronymsIntel IXP43X Product Line of Network Processors Datasheet Intel IXP400 Software Specification Update1.4 Overview Table 1. List of Acronyms and Abbreviations Sheet 2 of16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.0 System Architecture 2.1 System Architecture Description2.2 System Memory Map JTAG HeaderProcessors Memory Bus3.1 Soft Fusible Features 3.0 General Hardware Design ConsiderationsTable 2. Signal Type Definitions Soft Fusible Features Sheet 1 of3.2 DDRII/I SDRAM Interface Soft Fusible Features Sheet 2 of3.2.1 Signal Interface DDRII/I SDRAM Interface Pin Description Sheet 1 of3.2.2 DDRII/I SDRAM Initialization DDRII/I SDRAM Interface Pin Description Sheet 2 of3.3.1 Signal Interface 3.3 Expansion BusExpansion Bus Signal Recommendations Sheet 1 of 3.3.2 Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2 ofBoot/Reset Strapping Configuration Sheet 1 of Boot/Reset Strapping Configuration Sheet 2 of Network Processors Developer’s Manual3.3.3 8-Bit Device Interface Setting Intel XScale Processor Operation Speed3.3.4 16-Bit Device Interface AprilDocument Number 316844 Revision 001US Byte Access 16-Bit-Word AccessIntel IXP43X Product Line of NetworkIntel Flash 3.4 UART Interface16-Bit-Word Access 16-Bit Device3.4.1 Signal Interface UART Signal RecommendationsConnector Female 1 DCD2 RX 3 TX3.5.1 Signal Interface MII MII NPE A Signal RecommendationsMII NPE C Signal Recommendations Sheet 1 of being disabled without asserting a system reset3.5.2 Device Connection, MII MII NPE C Signal Recommendations Sheet 2 ofMAC Management Signal Recommendations - NPE A and NPE C being disabled without asserting a system reset3.6 GPIO Interface Network Processors10/100 Intel IXP43X3.6.1 Signal Interface 3.7 USB Interface3.6.2 Design Notes GPIO Signal Recommendations3.7.1 Signal Interface USB Host Signal RecommendationsFigure 7. Common Mode Choke USB RBIASP USB RBIASN22.6 Ω ±1 % resistor3.8.1 Signal Interface 3.8 UTOPIA Level 2 InterfaceUTOPIA Level 2/MIIA Type PullName DescriptionType PullName DescriptionType PullName Description3.9 HSS Interface 3.8.2 Device ConnectionIntel IXP43X Product Line of3.9.1 Signal Interface 3.9.2 Device Connectionbeing disabled without asserting a system reset High-Speed, Serial Interface3.10 SSP Interface Figure 11. HSS Interface Example3.10.1 Signal Interface 3.10.2 Device ConnectionSynchronous Serial Peripheral Port Interface 3.11 PCI Interface Intel IXP43X ProductLine of Network Processors3.11.1 Signal Interface PCI Controller Sheet 1 of3.11.2 PCI Interface Block Diagram PCI Controller Sheet 2 of3.11.3 PCI Option Interface Network ProcessorsFigure 13. PCI Interface Table 18. PCI Host/Option Interface Pin Description Sheet 1 ofPCI Host/Option Interface Pin Description Sheet 2 of TypeOption Name3.12 JTAG Interface 3.11.4 Design NotesPCI Host/Option Interface Pin Description Sheet 3 of 3.12.1 Signal Interface 3.13.1 Clock Signals3.13 Input System Clock 3.13.2 Clock OscillatorNetwork 3.13.3 Recommendations for Crystal SelectionOSCIN 33 KΩ3.14 Power Power SupplyProcessors Datasheet Processors Datasheet3.14.5 Power Sequence 3.14.6 Reset Timing3.14.1 Decoupling Capacitance Recommendations 3.14.2 VCC DecouplingThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.4 Component Placement 4.0 General PCB Guide4.1 PCB Overview 4.2 General Recommendations4.5 Stack-Up Selection InexpensiveManufactured by virtually all printed-circuit-board vendors Figure 16. Component Placement on a PCBPoor routing density Uncontrolled signal trace impedance Lack of power/ground planes, resulting in unacceptable crosstalkControlled-impedance traces Low-impedance power distribution Higher cost More weight Manufactured by fewer vendorsFigure 17. 8-Layer Stackup Figure 18. 6-Layer Stackup5.0 General Layout and Routing Guide 5.1 Overview5.2 General Layout Guidelines VIAs 5.2.1 General Component SpacingFigure 19. Signal Changing Reference Planes Figure 20. Good Design Practice for VIA Hole Placement Figure 21. Poor Design Practice for VIA Placement25 mils min 25 mils min 25 mils min Flush Via min Potential Bridge min5.2.2 Clock Signal Considerations PBGA PackageFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.3 MII Signal Considerations 5.2.4 USB V2.0 Considerations5.2.5 Crosstalk 5.2.8 Power and Ground Plane 5.2.6 EMI Design Considerations5.2.7 Trace Impedance Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.0 PCI Interface Design Considerations 6.1 Electrical Interface6.2 Topology 6.3 Clock Distribution PCI SlotPCI Slot PCI Slot6.3.1 Trace Length Limits PCI DevicesClock Driver6.3.3 Signal Loading 6.3.2 Routing GuidelinesThis manual does not repeat all the guidelines that are already stated in the 7.0 DDRII / DDRI SDRAM 7.1 IntroductionDDRII/I Signal Groups Signal NameGroup DescriptionDDR SDRAM ProcessorsProduct Line of Network IXP43XSupported DDRI 32-bit SDRAM Configurations Supported DDRII 32-bit SDRAM ConfigurationsSupported DDRI 16-bit SDRAM Configurations DDRI R1 =387 Ω ±1 % resistorR 1 = 285 Ω ±1 % resistor DDRIMPCRES7.3 DDRII OCD Pin Requirements 7.3.1 Signal-Timing AnalysisFigure 27. DDRII OCD Pin Requirements Figure 28. DDR Clock Timing WaveformFigure 29. DDR SDRAM Write Timings Figure 30. DDR SDRAM Read TimingsADDR/CTRL CS10# CK DQS DQS # DQDDRII-400 MHz Interface -- Signal Timings Figure 31. DDR - Write Preamble/Postamble DurationSee Figure 29, “DDR SDRAM Write Timings” on page 7.3.2 Timing Relationships DDR II/I SDRAM Interface -- Signal Timings7.3.1.0.1 Printed Circuit Board Layer Stackup Signal Package Lengths Sheet 1 of Table 31 on pageTable 32 on page Table 33 on page Figure 30 on page Table 32 on pageSignal Package Lengths Sheet 2 of Signal NameSignal Name Group7.3.3 Routing Guidelines 7.3.3.1 Clock GroupSignal Package Lengths Sheet 3 of 7.3.3.2 Data and Control Groups Figure 32. DDRII Clock Simulation Results CK SignalsClock Signal Group Routing Guidelines 22 ohm Table 35. DDRII Data and Control Signal Group Routing Guidelines7.3.3.3 Command Groups 20ohmTable 35. DDRII Data and Control Signal Group Routing Guidelines Figure 34. DDRII Command Simulation Results ADDRESS signalsTable 36. DDRII Command Signal Group Routing Guidelines