Device Connection, MII | Intel IXP43X instruction

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Table 10.			MII NPE C Signal Recommendations (Sheet 2 of 2)

		Name			Type	Pull
					Type	Up/	Recommendations
					Field	Up/	Recommendations
					Field	Down
						Down

							Externally supplied receive clock:
							• 25 MHz for 100 Mbps operation
	ETHC_rxclk				I	Yes	• 2.5 MHz for 10 Mbps
							This MAC contains hardware hashing capabilities that are local to the interface.
							Should be pulled high through a 10-KΩresistor when not being utilized in the system.

							Receive data bus from PHY, data sampled synchronously, with respect to ETHC_RXCLK.
	ETHC_rxdATA[3:0]				I	Yes	This MAC contains hardware hashing capabilities that are local to the interface.
							Should be pulled high through a 10-KΩresistor when not being utilized in the system.

							Receive data valid is used to inform the MII interface about data that is being sent by
	ETHC_rxdv				I	Yes	the Ethernet PHY
	ETHC_rxdv				I	Yes	This MAC contains hardware hashing capabilities that are local to the interface.

							Should be pulled high through a 10-KΩresistor when not being utilized in the system.

							Asserted by the PHY when a collision is detected by the PHY. This MAC contains
							hardware hashing capabilities that are local to the interface.
	ETHC_col				I	Yes	Should be pulled high through a 10-KΩresistor when not being utilized in the system
	ETHC_col				I	Yes	When this interface is disabled through the NPE-C Ethernet soft fuse (refer to the
							Expansion Bus Controller chapter of the Intel® IXP43X Product Line of Network
							Processors Developer’s Manual) and is not being used a system design, this interface/
							signal is not required for any connection.

							Asserted by the PHY when the transmit medium or receive medium are active.
							De-asserted when both the transmit and receive medium are idle. Remains asserted
	ETHC_crs				I	Yes	throughout the duration of collision condition. PHY asserts CRS asynchronously and
	ETHC_crs				I	Yes	de-asserts synchronously with respect to ETHC_RXCLK.
							This MAC contains hardware hashing capabilities that are local to the interface.
							Should be pulled high through a 10-KΩresistor when not being utilized in the system.

	Notes:
	1.	Features disabled/enabled by Soft Fuse must be done during the boot-up sequence. A feature cannot be enabled after
		being disabled without asserting a system reset.
	2.	Features disabled by a specific part number, do not require pull-ups or pull-downs. Therefore, all pins can be left
		unconnected.
	3.	Features enabled by a specific part number — and required to be Soft Fuse-disabled, as stated in note 1 — only require
		pull-ups or pull-downs in the clock-input signals.

Table 11.		MAC Management Signal Recommendations - NPE A and NPE C

	Name	Type	Pull
		Type	Up/	Recommendations
		Field	Up/	Recommendations
		Field	Down
			Down

				NPE A and NPE C
				Management data input output. Provides the write data to both PHY devices connected to
	ETH_mdio	IO	Yes	each MII interface. An external pull-up resistor of 1.5K ohm is required on
	ETH_mdio	IO	Yes	ETHC_MDIO to properly quantify the external PHYs used in the system. For specific

				implementation, see the IEEE 802.3 specification.
				Should be pulled high through a 10-KΩresistor when not being utilized in the system

				NPE A and NPE C
	ETH_mdc	O	No	Management data clock. Management data interface clock is used to clock the MDIO signal as
	ETH_mdc	O	No	an output and sample the MDIO as an input. The ETHC_MDC is an input on power up and can
				be configured to be an output through Intel APIs documented in the Intel® IXP400 Software
				Programmer’s Guide

3.5.2Device Connection, MII

Figure 6 is a typical example of an Ethernet PHY device interfacing to one of the MACs via the MII hardware protocol.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	31

Image 31

Intel IXP43X manual Device Connection, MII, MII NPE C Signal Recommendations Sheet 2

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network Processors HDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Chapter Name Description Content Overview Term Explanation Related DocumentationAcronyms List of Acronyms and Abbreviations Sheet 1 List of Acronyms and Abbreviations Sheet 2 Overview HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Memory Map System Architecture Description Intel IXP43X Product Symbol Description Soft Fusible FeaturesSignal Type Definitions Soft Fusible Features Sheet 1 Ethernet Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately DDRII/I Sdram Interface Name Device-Pin Connection Terminatio Description Field Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Type DDRII/I Sdram Interface Pin Description Sheet 2 DDRII/I Sdram Initialization Expansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Name Type Pull Recommendations Field Down Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Boot/Reset Strapping Configuration Sheet 1 Boot/Reset Strapping Configuration Sheet 2 MHz Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed 4 16-Bit Device Interface 16-Bit Device Interface Flash Interface Flash Interface Example Uart Interface Uart Signal Recommendations Uart Interface Example MII Interface MII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII MII Interface Example Gpio Interface USB Interface Gpio Signal RecommendationsDesign Notes Name Type Pull Description Field Down USB Host Signal Recommendations Common Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down Utpopfci UTPOPDATA4UTPOPDATA75 UTPOPADDR40 ETHARXDATA30 Etharxclk ClavUtpipfci Utpipsoc UTPIPADDR40 UTPIPDATA5UTPIPDATA6 UTPIPDATA7 Device Connection HSS Interface HSSRXDATA0 High-Speed, Serial InterfaceHSSTXDATA0 HSSTXCLK0 HSS Interface Example SSP Interface Synchronous Serial Peripheral Port Interface Serial Flash and SSP Port SPI Interface Example PCI Interface PCI Controller Sheet 1 Pciclkin PCI Interface Block DiagramPCI Controller Sheet 2 Pciintan Type Option Description Name Device-Pin Connection Field Connect signal to same pin between PCI Parity Two devicesPCI Option Interface PCI Host/Option Interface Pin Description Sheet 1 Type Option Name Device-Pin Connection Description Field On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host PCI Host/Option Interface Pin Description Sheet 2 PCI Host/Option Interface Pin Description Sheet 3 Jtag Interface Clock Oscillator Clock SignalsClock Signals Input System Clock Recommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description VCC Decoupling Power SequenceReset Timing Decoupling Capacitance Recommendations § § Component Selection Component PlacementPCB Overview General Recommendations Stack-Up Selection Component Placement on a PCB Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout Guidelines General Layout and Routing Guide General Component Spacing Signal Changing Reference Planes Good Design Practice for VIA Hole Placement Pad-to-Pad Clearance of Passive Components to a PGA or BGA Clock Signal Considerations USB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec Electrical InterfaceTopology @33 MHz PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines PCI Clock Routing Guidelines Trace Length Limits Routing Guidelines Signal Loading Introduction Ddrii / Ddri Sdram Dcasn / Ddrcasn DDRII/I Signal GroupsGroup Signal Name Description Drasn / Ddrrasn DDR Sdram Sizea Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Supported Ddri 16-bit Sdram Configurations Technology Arrangement Banks Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Address Size Leaf Select Total Ddrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings Symbol Parameter Minimum Nominal Maximum Units DDRII-400 MHz Interface -- Signal Timings Printed Circuit Board Layer Stackup DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Timing Relationships Group Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Clock Group Signal Package Lengths Sheet 3 Parameter Definition Data and Control Groups DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Data and Control Signal Group Routing Guidelines Signal Group Members Ddrii Command Signal Group Routing Guidelines § §