Intel IXP43X manual Tables, Pad-to-Pad Clearance of Passive Components to a PGA or BGA

Models: IXP43X

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Pad-to-Pad Clearance of Passive Components to a PGA or BGA

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

11

HSS Interface Example

42

12

Serial Flash and SSP Port (SPI) Interface Example

44

13

PCI Interface

47

14

Clock Oscillator Interface Example

51

15

Recommended circuit design on PCB for crystal oscillator

52

16

Component Placement on a PCB

56

17

8-Layer Stackup

58

18

6-Layer Stackup

58

19

Signal Changing Reference Planes

60

20

Good Design Practice for VIA Hole Placement

61

21

Poor Design Practice for VIA Placement

61

22

Pad-to-Pad Clearance of Passive Components to a PGA or BGA

62

23

PCI Address/Data Topology

67

24

PCI Clock Topology

68

25

Processor-DDRII/I SDRAM Interface

72

26

DDRII/DDRI RCOMP Pin External Resistor Requirements

74

27

DDRII OCD Pin Requirements

75

28

DDR Clock Timing Waveform

75

29

DDR SDRAM Write Timings

76

30

DDR SDRAM Read Timings

76

31

DDR - Write Preamble/Postamble Duration

77

32

DDRII Clock Simulation Results: CK Signals

82

33

DDRII Data and Control Simulation Results: DQ and DQS signals

83

34

DDRII Command Simulation Results: ADDRESS signals

84

Tables

 

1

List of Acronyms and Abbreviations

10

2

Signal Type Definitions

17

3

Soft Fusible Features

17

4

DDRII/I SDRAM Interface Pin Description

19

5

Expansion Bus Signal Recommendations

21

6

Boot/Reset Strapping Configuration

22

7

Setting Intel XScale® Processor Operation Speed

24

8

UART Signal Recommendations

27

9

MII NPE A Signal Recommendations

29

10

MII NPE C Signal Recommendations

29

11

MAC Management Signal Recommendations NPE A and NPE C

30

12

GPIO Signal Recommendations

32

13

USB Host Signal Recommendations

33

14

UTOPIA Level 2/MII_A

36

15

High-Speed, Serial Interface 0

41

16

Synchronous Serial Peripheral Port Interface

43

17

PCI Controller

45

18

PCI Host/Option Interface Pin Description

47

19

Synchronous Serial Peripheral Port Interface

50

20

Clock Signals

50

21

Power Supply

52

22

PCI Address/Data Routing Guidelines

67

23

PCI Clock Routing Guidelines

68

24

DDRII/I Signal Groups

71

25

Supported DDRI 32-bit SDRAM Configurations

73

26

Supported DDRII 32-bit SDRAM Configurations

73

27

Supported DDRI 16-bit SDRAM Configurations

73

28

Supported DDRII 16-bit SDRAM Configurations

74

 

Intel® IXP43X Product Line of Network Processors

April 2007

HDG

Document Number: 316844; Revision: 001US

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Intel IXP43X manual Tables, Pad-to-Pad Clearance of Passive Components to a PGA or BGA