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Intel manual PCI Interface, Intel IXP43X Product, Line of Network, Processors, SPI Flash

Models: IXP43X

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Intel® IXP43X Product

Hardware Design Guidelines—Intel®IXP43X Product Line of Network Processors

Figure 12. Serial Flash and SSP Port (SPI) Interface Example

	Intel® IXP43X Product

	Line of Network						SPI Flash
	Processors

	SSP_SCLK						CLK

	SSP_SFRM						CS_N

	SSP_TXD						D I

	SSP_RXD						DO

SSP_EXTCLK

7.2 KHz to 3.6864 MHz

SSP Interface

External Oscillator

B4109 -003

3.11PCI Interface

The PCI Controller of the IXP43X network processors is an industry-standard, 32-bit interface, high-performance bus that operates at 33 MHz(PCI Local Bus Specification, Rev. 2.2).

The PCI interface is capable of operating as a host or an option. This PCI implementation supports 3.3 V I/O only.

As indicated in Figure 13, a PCI transparent bridge is required to support Compact PCI.

General PCI routing guidelines can be found in Section 6.2, “Topology” on page 67. For detailed information, see the PCI Local Bus Specification, Rev. 2.2.

	Intel® IXP43X Product Line of Network Processors
April 2007	HDG
Document Number: 316844; Revision: 001US	45

Image 45

Intel manual PCI Interface, Intel IXP43X Product, Line of Network, Processors, SPI Flash, SSP Interface

Contents

Hardware Design Guidelines Intel IXP43X Product Line of Network ProcessorsApril April Intel IXP43X Product Line of Network ProcessorsIntroduction ContentsFigures DDRII Data and Control Simulation Results DQ and DQS signals TablesMAC Management Signal Recommendations NPE A and NPE C Pad-to-Pad Clearance of Passive Components to a PGA or BGADDR Clock Timings April Revision HistoryIntel IXP43X Product Line of Network Processors AprilDocument Number 316844 Revision 001US 1.0 Introduction 1.1 Content Overview1.3 Acronyms 1.2 Related DocumentationIntel IXP43X Product Line of Network Processors Datasheet Intel IXP400 Software Specification UpdateTable 1. List of Acronyms and Abbreviations Sheet 2 of 1.4 Overview16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.0 System Architecture 2.1 System Architecture Description2.2 System Memory Map Header JTAGProcessors Memory Bus3.0 General Hardware Design Considerations 3.1 Soft Fusible FeaturesTable 2. Signal Type Definitions Soft Fusible Features Sheet 1 ofSoft Fusible Features Sheet 2 of 3.2 DDRII/I SDRAM InterfaceDDRII/I SDRAM Interface Pin Description Sheet 1 of 3.2.1 Signal InterfaceDDRII/I SDRAM Interface Pin Description Sheet 2 of 3.2.2 DDRII/I SDRAM Initialization3.3.1 Signal Interface 3.3 Expansion BusExpansion Bus Signal Recommendations Sheet 1 of 3.3.2 Reset Configuration Straps Expansion Bus Signal Recommendations Sheet 2 ofBoot/Reset Strapping Configuration Sheet 1 of Network Processors Developer’s Manual Boot/Reset Strapping Configuration Sheet 2 ofSetting Intel XScale Processor Operation Speed 3.3.3 8-Bit Device Interface3.3.4 16-Bit Device Interface AprilDocument Number 316844 Revision 001US 16-Bit-Word Access Byte AccessIntel IXP43X Product Line of Network3.4 UART Interface Intel Flash16-Bit-Word Access 16-Bit DeviceUART Signal Recommendations 3.4.1 Signal Interface1 DCD Connector Female2 RX 3 TXMII NPE A Signal Recommendations 3.5.1 Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 of being disabled without asserting a system resetMII NPE C Signal Recommendations Sheet 2 of 3.5.2 Device Connection, MIIMAC Management Signal Recommendations - NPE A and NPE C being disabled without asserting a system resetNetwork Processors 3.6 GPIO Interface10/100 Intel IXP43X3.7 USB Interface 3.6.1 Signal Interface3.6.2 Design Notes GPIO Signal RecommendationsUSB Host Signal Recommendations 3.7.1 Signal InterfaceFigure 7. Common Mode Choke USB RBIASN USB RBIASP22.6 Ω ±1 % resistor3.8.1 Signal Interface 3.8 UTOPIA Level 2 InterfaceUTOPIA Level 2/MIIA Pull TypeName DescriptionPull TypeName DescriptionPull TypeName Description3.8.2 Device Connection 3.9 HSS InterfaceIntel IXP43X Product Line of3.9.2 Device Connection 3.9.1 Signal Interfacebeing disabled without asserting a system reset High-Speed, Serial InterfaceFigure 11. HSS Interface Example 3.10 SSP Interface3.10.1 Signal Interface 3.10.2 Device ConnectionSynchronous Serial Peripheral Port Interface Intel IXP43X Product 3.11 PCI InterfaceLine of Network ProcessorsPCI Controller Sheet 1 of 3.11.1 Signal InterfacePCI Controller Sheet 2 of 3.11.2 PCI Interface Block DiagramNetwork Processors 3.11.3 PCI Option InterfaceFigure 13. PCI Interface Table 18. PCI Host/Option Interface Pin Description Sheet 1 ofType PCI Host/Option Interface Pin Description Sheet 2 ofOption Name3.12 JTAG Interface 3.11.4 Design NotesPCI Host/Option Interface Pin Description Sheet 3 of 3.13.1 Clock Signals 3.12.1 Signal Interface3.13 Input System Clock 3.13.2 Clock Oscillator3.13.3 Recommendations for Crystal Selection NetworkOSCIN 33 KΩPower Supply 3.14 PowerProcessors Datasheet Processors Datasheet3.14.6 Reset Timing 3.14.5 Power Sequence3.14.1 Decoupling Capacitance Recommendations 3.14.2 VCC DecouplingThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.0 General PCB Guide 4.4 Component Placement4.1 PCB Overview 4.2 General RecommendationsInexpensive 4.5 Stack-Up SelectionManufactured by virtually all printed-circuit-board vendors Figure 16. Component Placement on a PCBLack of power/ground planes, resulting in unacceptable crosstalk Poor routing density Uncontrolled signal trace impedanceControlled-impedance traces Low-impedance power distribution Higher cost More weight Manufactured by fewer vendorsFigure 18. 6-Layer Stackup Figure 17. 8-Layer Stackup5.0 General Layout and Routing Guide 5.1 Overview5.2 General Layout Guidelines VIAs 5.2.1 General Component SpacingFigure 19. Signal Changing Reference Planes Figure 21. Poor Design Practice for VIA Placement Figure 20. Good Design Practice for VIA Hole Placement25 mils min 25 mils min 25 mils min Flush Via min Potential Bridge min5.2.2 Clock Signal Considerations PBGA PackageFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.3 MII Signal Considerations 5.2.4 USB V2.0 Considerations5.2.5 Crosstalk 5.2.8 Power and Ground Plane 5.2.6 EMI Design Considerations5.2.7 Trace Impedance Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.0 PCI Interface Design Considerations 6.1 Electrical Interface6.2 Topology PCI Slot 6.3 Clock DistributionPCI Slot PCI SlotPCI Devices 6.3.1 Trace Length LimitsClock Driver6.3.3 Signal Loading 6.3.2 Routing GuidelinesThis manual does not repeat all the guidelines that are already stated in the 7.1 Introduction 7.0 DDRII / DDRI SDRAMSignal Name DDRII/I Signal GroupsGroup DescriptionProcessors DDR SDRAMProduct Line of Network IXP43XSupported DDRI 32-bit SDRAM Configurations Supported DDRII 32-bit SDRAM ConfigurationsSupported DDRI 16-bit SDRAM Configurations R1 =387 Ω ±1 % resistor DDRIR 1 = 285 Ω ±1 % resistor DDRIMPCRES7.3.1 Signal-Timing Analysis 7.3 DDRII OCD Pin RequirementsFigure 27. DDRII OCD Pin Requirements Figure 28. DDR Clock Timing WaveformFigure 30. DDR SDRAM Read Timings Figure 29. DDR SDRAM Write TimingsADDR/CTRL CS10# CK DQS DQS # DQDDRII-400 MHz Interface -- Signal Timings Figure 31. DDR - Write Preamble/Postamble DurationSee Figure 29, “DDR SDRAM Write Timings” on page 7.3.2 Timing Relationships DDR II/I SDRAM Interface -- Signal Timings7.3.1.0.1 Printed Circuit Board Layer Stackup Table 31 on page Signal Package Lengths Sheet 1 ofTable 32 on page Table 33 on page Figure 30 on page Table 32 on pageSignal Name Signal Package Lengths Sheet 2 ofSignal Name Group7.3.3 Routing Guidelines 7.3.3.1 Clock GroupSignal Package Lengths Sheet 3 of 7.3.3.2 Data and Control Groups Figure 32. DDRII Clock Simulation Results CK SignalsClock Signal Group Routing Guidelines Table 35. DDRII Data and Control Signal Group Routing Guidelines 22 ohm20ohm 7.3.3.3 Command GroupsTable 35. DDRII Data and Control Signal Group Routing Guidelines Figure 34. DDRII Command Simulation Results ADDRESS signalsTable 36. DDRII Command Signal Group Routing Guidelines