Manuals / Intel / Computer Equipment / Computer Hardware

Intel IXP43X manual DDRII Command Signal Group Routing Guidelines

Models: IXP43X

1 86

Download 86 pages 24.53 Kb

Page 86

Manual background

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 36. DDRII Command Signal Group Routing Guidelines

Parameter	Definition

Series Resistor	20 Ω

Nominal Trace Width1	Internal (Strip Line) 3.5 mils, External (Micro Strip) 5 mils
Nominal Pair Spacing (edge to edge) 2	Internal (Strip Line) 10.5 mils, External (Micro Strip) 10 mils
Minimum Pair to Pair Spacing	Any layer 20mils

Minimum Spacing to Other DDR Signals	20.0 mils

Minimum Spacing to non-DDR Signals	25.0 mils

Maximum Via Count	5 per trace

Total Trace Length	1500 mils to 2500 mils

Notes:

1. Nominal trace width is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zo.

2. Nominal pair to pair spacing is determined by board physical characteristics and stack-up. This value should be verified with the PWB manufacturer to achieve the desired Zdiff.

§ §

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
86	Document Number: 316844; Revision: 001US

Image 86

Intel IXP43X manual DDRII Command Signal Group Routing Guidelines

Contents

April Hardware Design GuidelinesIntel IXP43X Product Line of Network Processors Intel IXP43X Product Line of Network Processors AprilContents IntroductionFigures MAC Management Signal Recommendations NPE A and NPE C TablesDDRII Data and Control Simulation Results DQ and DQS signals Pad-to-Pad Clearance of Passive Components to a PGA or BGADDR Clock Timings Revision History AprilDocument Number 316844 Revision 001US Intel IXP43X Product Line of Network ProcessorsApril 1.1 Content Overview 1.0 IntroductionIntel IXP43X Product Line of Network Processors Datasheet 1.2 Related Documentation1.3 Acronyms Intel IXP400 Software Specification Update1.4 Overview Table 1. List of Acronyms and Abbreviations Sheet 2 of16 GPIO General Purpose Input Output Packaging 460-pin PBGA Figure 1. Intel IXP435 Network Processor Block Diagram 1.5 Typical Applications 2.2 System Memory Map 2.0 System Architecture2.1 System Architecture Description Processors JTAGHeader Memory BusTable 2. Signal Type Definitions 3.1 Soft Fusible Features3.0 General Hardware Design Considerations Soft Fusible Features Sheet 1 of3.2 DDRII/I SDRAM Interface Soft Fusible Features Sheet 2 of3.2.1 Signal Interface DDRII/I SDRAM Interface Pin Description Sheet 1 of3.2.2 DDRII/I SDRAM Initialization DDRII/I SDRAM Interface Pin Description Sheet 2 ofExpansion Bus Signal Recommendations Sheet 1 of 3.3.1 Signal Interface3.3 Expansion Bus Boot/Reset Strapping Configuration Sheet 1 of 3.3.2 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 of Boot/Reset Strapping Configuration Sheet 2 of Network Processors Developer’s Manual3.3.3 8-Bit Device Interface Setting Intel XScale Processor Operation SpeedDocument Number 316844 Revision 001US 3.3.4 16-Bit Device InterfaceApril Intel IXP43X Product Byte Access16-Bit-Word Access Line of Network16-Bit-Word Access Intel Flash3.4 UART Interface 16-Bit Device3.4.1 Signal Interface UART Signal Recommendations2 RX Connector Female1 DCD 3 TXMII NPE C Signal Recommendations Sheet 1 of 3.5.1 Signal Interface MIIMII NPE A Signal Recommendations being disabled without asserting a system resetMAC Management Signal Recommendations - NPE A and NPE C 3.5.2 Device Connection, MIIMII NPE C Signal Recommendations Sheet 2 of being disabled without asserting a system reset10/100 3.6 GPIO InterfaceNetwork Processors Intel IXP43X3.6.2 Design Notes 3.6.1 Signal Interface3.7 USB Interface GPIO Signal Recommendations3.7.1 Signal Interface USB Host Signal RecommendationsFigure 7. Common Mode Choke 22.6 Ω ±1 % USB RBIASPUSB RBIASN resistorUTOPIA Level 2/MIIA 3.8.1 Signal Interface3.8 UTOPIA Level 2 Interface Name TypePull DescriptionName TypePull DescriptionName TypePull DescriptionIntel IXP43X 3.9 HSS Interface3.8.2 Device Connection Product Line ofbeing disabled without asserting a system reset 3.9.1 Signal Interface3.9.2 Device Connection High-Speed, Serial Interface3.10 SSP Interface Figure 11. HSS Interface ExampleSynchronous Serial Peripheral Port Interface 3.10.1 Signal Interface3.10.2 Device Connection Line of Network 3.11 PCI InterfaceIntel IXP43X Product Processors3.11.1 Signal Interface PCI Controller Sheet 1 of3.11.2 PCI Interface Block Diagram PCI Controller Sheet 2 ofFigure 13. PCI Interface 3.11.3 PCI Option InterfaceNetwork Processors Table 18. PCI Host/Option Interface Pin Description Sheet 1 ofOption PCI Host/Option Interface Pin Description Sheet 2 ofType NamePCI Host/Option Interface Pin Description Sheet 3 of 3.12 JTAG Interface3.11.4 Design Notes 3.13 Input System Clock 3.12.1 Signal Interface3.13.1 Clock Signals 3.13.2 Clock OscillatorOSCIN Network3.13.3 Recommendations for Crystal Selection 33 KΩProcessors Datasheet 3.14 PowerPower Supply Processors Datasheet3.14.1 Decoupling Capacitance Recommendations 3.14.5 Power Sequence3.14.6 Reset Timing 3.14.2 VCC DecouplingThe IXP43X network processors can be configured at reset de-assertion via external, pull-down resistors on the address expansion bus signals EXADDR2321. For a complete description, see Section 6, “Boot/Reset Strapping Configuration” on page 4.1 PCB Overview 4.4 Component Placement4.0 General PCB Guide 4.2 General RecommendationsManufactured by virtually all printed-circuit-board vendors 4.5 Stack-Up SelectionInexpensive Figure 16. Component Placement on a PCBControlled-impedance traces Low-impedance power distribution Poor routing density Uncontrolled signal trace impedanceLack of power/ground planes, resulting in unacceptable crosstalk Higher cost More weight Manufactured by fewer vendorsFigure 17. 8-Layer Stackup Figure 18. 6-Layer Stackup5.2 General Layout Guidelines 5.0 General Layout and Routing Guide5.1 Overview Figure 19. Signal Changing Reference Planes VIAs5.2.1 General Component Spacing 25 mils min 25 mils min 25 mils min Figure 20. Good Design Practice for VIA Hole PlacementFigure 21. Poor Design Practice for VIA Placement Flush Via min Potential Bridge minFigure 22. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 5.2.2 Clock Signal ConsiderationsPBGA Package 5.2.5 Crosstalk 5.2.3 MII Signal Considerations5.2.4 USB V2.0 Considerations 5.2.7 Trace Impedance 5.2.8 Power and Ground Plane5.2.6 EMI Design Considerations Use at least one decoupling capacitor per power pin and place it as close as possible to the pin 6.2 Topology 6.0 PCI Interface Design Considerations6.1 Electrical Interface PCI Slot 6.3 Clock DistributionPCI Slot PCI SlotClock 6.3.1 Trace Length LimitsPCI Devices DriverThis manual does not repeat all the guidelines that are already stated in the 6.3.3 Signal Loading6.3.2 Routing Guidelines 7.0 DDRII / DDRI SDRAM 7.1 IntroductionGroup DDRII/I Signal GroupsSignal Name DescriptionProduct Line of Network DDR SDRAMProcessors IXP43XSupported DDRI 16-bit SDRAM Configurations Supported DDRI 32-bit SDRAM ConfigurationsSupported DDRII 32-bit SDRAM Configurations R 1 = 285 Ω ±1 % resistor DDRIR1 =387 Ω ±1 % resistor DDRIMPCRESFigure 27. DDRII OCD Pin Requirements 7.3 DDRII OCD Pin Requirements7.3.1 Signal-Timing Analysis Figure 28. DDR Clock Timing WaveformADDR/CTRL Figure 29. DDR SDRAM Write TimingsFigure 30. DDR SDRAM Read Timings CS10# CK DQS DQS # DQSee Figure 29, “DDR SDRAM Write Timings” on page DDRII-400 MHz Interface -- Signal TimingsFigure 31. DDR - Write Preamble/Postamble Duration 7.3.1.0.1 Printed Circuit Board Layer Stackup 7.3.2 Timing RelationshipsDDR II/I SDRAM Interface -- Signal Timings Table 32 on page Table 33 on page Signal Package Lengths Sheet 1 ofTable 31 on page Figure 30 on page Table 32 on pageSignal Name Signal Package Lengths Sheet 2 ofSignal Name GroupSignal Package Lengths Sheet 3 of 7.3.3 Routing Guidelines7.3.3.1 Clock Group Clock Signal Group Routing Guidelines 7.3.3.2 Data and Control GroupsFigure 32. DDRII Clock Simulation Results CK Signals 22 ohm Table 35. DDRII Data and Control Signal Group Routing GuidelinesTable 35. DDRII Data and Control Signal Group Routing Guidelines 7.3.3.3 Command Groups20ohm Figure 34. DDRII Command Simulation Results ADDRESS signalsTable 36. DDRII Command Signal Group Routing Guidelines