Clock Group, Signal Package Lengths Sheet 3 | Intel IXP43X specification

Intel® IXP43X Product Line of Network Processors—Hardware Design Guidelines

Table 33.	Signal Package Lengths (Sheet 3 of 3)

	Group	Signal Name	Length (mil)		Signal Name	Length (mil)

		D_MA0 / DDR_MA0	515.78		D_MA7 / DDR_MA7	438.95

		D_MA1 / DDR_MA1	357.69		D_MA8 / DDR_MA8	394.65

		D_MA2 / DDR_MA2	509.12		D_MA9 / DDR_MA9	429.78

		D_MA3 / DDR_MA3	462.16		D_MA10 /	378.96
		D_MA3 / DDR_MA3	462.16		DDR_MA10	378.96
					DDR_MA10

		D_MA4 / DDR_MA4	444.71		D_MA11 /	418.37
		D_MA4 / DDR_MA4	444.71		DDR_MA11	418.37
					DDR_MA11

	Command	D_MA5 / DDR_MA5	576.87		D_MA12 /	392.79
		D_MA5 / DDR_MA5	576.87		DDR_MA12	392.79
					DDR_MA12

		D_MA6 / DDR_MA6	513.40		D_MA13 /	433.55
		D_MA6 / DDR_MA6	513.40		DDR_MA13	433.55
					DDR_MA13

		D_BA0 / DDR_BA0	530.35		D_BA1 / DDR_BA1	535.27

		D_RAS_N /	506.35		D_CAS_N /	477.26
		DDR_RAS_N	506.35		DDR_CAS_N	477.26
		DDR_RAS_N			DDR_CAS_N

		D_WE_N /	513.09
		DDR_WE_N	513.09
		DDR_WE_N

7.3.3Routing Guidelines

7.3.3.1Clock Group

The clock signal group includes the differential clock pairs D_CK[2:0] / DDR_CK[2:0] and D_CK_N[2:0] / DDR_CK_N[2:0].

Here are some tips on how to route the differential clock pairs:

•Ensure that DDR clocks are routed on a single internal layers, except for pin escapes

•A ground plane must be adjacent to the layer where the signals are routed

•Minimize the number of vias used, but ensure that the same number of vias are used in the positive and negative trace

•It is recommended that pin escape vias be located directly adjacent to the ball pads on all clocks

•Traces must be routed for differential mode impedance of 120 Ω

•Surface layer routing should be minimized (top or bottom layers)

•It is recommended to perform pre- and post-layout simulation

A series resistance value in the 25- to 50-Ωrange should be used as it adds minimal propagation delay to the signal without adversely varying from the CLK plus DQ propagation delay average. The appropriate value for termination resistance should be verified through simulation for the specific topology.

Table 34 provides routing guidelines for signals within this group.

Intel® IXP43X Product Line of Network Processors
HDG	April 2007
82	Document Number: 316844; Revision: 001US

Image 82

Intel IXP43X manual Clock Group, Signal Package Lengths Sheet 3

Contents

Intel IXP43X Product Line of Network Processors Hardware Design Guidelines HDG Intel IXP43X Product Line of Network ProcessorsApril Contents Figures Tables Document Number 316844 Revision 001US Date Revision Description § §001 Initial release HDG Content Overview Chapter Name Description List of Acronyms and Abbreviations Sheet 1 Related DocumentationAcronyms Term Explanation Overview List of Acronyms and Abbreviations Sheet 2 HDG Intel IXP435 Network Processor Block Diagram Typical Applications System Architecture Description System Memory Map Intel IXP43X Product Soft Fusible Features Sheet 1 Soft Fusible FeaturesSignal Type Definitions Symbol Description DDRII/I Sdram Interface Soft Fusible Features Sheet 2USB Host Each USB can be Enable separately Ethernet Type Signal InterfaceDDRII/I Sdram Interface Pin Description Sheet 1 Name Device-Pin Connection Terminatio Description Field DDRII/I Sdram Initialization DDRII/I Sdram Interface Pin Description Sheet 2 Expansion Bus Expansion Bus Signal Recommendations Sheet 1Type Pull Name Recommendations Field Down Boot/Reset Strapping Configuration Sheet 1 Reset Configuration StrapsExpansion Bus Signal Recommendations Sheet 2 Name Type Pull Recommendations Field Down Boot/Reset Strapping Configuration Sheet 2 Intel XScale Processor Cfg0 Cfg1 Cfgenn Actual Core Speed Setting Intel XScale Processor Operation Speed3 8-Bit Device Interface MHz 4 16-Bit Device Interface Flash Interface 16-Bit Device Interface Uart Interface Flash Interface Example Uart Signal Recommendations MII Interface Uart Interface Example MII NPE a Signal Recommendations Signal Interface MIIMII NPE C Signal Recommendations Sheet 1 MAC Management Signal Recommendations NPE a and NPE C MII NPE C Signal Recommendations Sheet 2Device Connection, MII Gpio Interface MII Interface Example USB Interface Gpio Signal RecommendationsDesign Notes USB Host Signal Recommendations Name Type Pull Description Field Down Common Mode Choke Host Device Utopia Level 2/MIIA Utopia Level 2 InterfaceType Pull Name Description Field Down UTPOPADDR40 UTPOPDATA4UTPOPDATA75 Utpopfci Utpipsoc ClavUtpipfci ETHARXDATA30 Etharxclk UTPIPDATA7 UTPIPDATA5UTPIPDATA6 UTPIPADDR40 HSS Interface Device Connection HSSTXCLK0 High-Speed, Serial InterfaceHSSTXDATA0 HSSRXDATA0 SSP Interface HSS Interface Example Synchronous Serial Peripheral Port Interface PCI Interface Serial Flash and SSP Port SPI Interface Example PCI Controller Sheet 1 Pciintan PCI Interface Block DiagramPCI Controller Sheet 2 Pciclkin PCI Host/Option Interface Pin Description Sheet 1 Connect signal to same pin between PCI Parity Two devicesPCI Option Interface Type Option Description Name Device-Pin Connection Field PCI Host/Option Interface Pin Description Sheet 2 On the Option device, these signals are notSignal PCIREQN0 to one PCIREQN30 inputs to the Host Type Option Name Device-Pin Connection Description Field Jtag Interface PCI Host/Option Interface Pin Description Sheet 3 Input System Clock Clock SignalsClock Signals Clock Oscillator Recommendations for Crystal Selection Power Supply PowerNominal Name Voltage Description Decoupling Capacitance Recommendations Power SequenceReset Timing VCC Decoupling § § General Recommendations Component PlacementPCB Overview Component Selection Component Placement on a PCB Stack-Up Selection Controlled-impedance traces Low-impedance power distribution Layer Stackup General Layout and Routing Guide General Layout Guidelines Signal Changing Reference Planes General Component Spacing Good Design Practice for VIA Hole Placement Clock Signal Considerations Pad-to-Pad Clearance of Passive Components to a PGA or BGA USB V2.0 Considerations MII Signal ConsiderationsCrosstalk EMI Design Considerations Power and Ground PlaneTrace Impedance § § @33 MHz Electrical InterfaceTopology Tcyc = 30 nSec Tval = 11 nSec Tprop = 10 nSec PCI Address/Data Routing Guidelines Clock DistributionParameter Routing Guidelines Trace Length Limits PCI Clock Routing Guidelines Signal Loading Routing Guidelines Ddrii / Ddri Sdram Introduction Drasn / Ddrrasn DDRII/I Signal GroupsGroup Signal Name Description Dcasn / Ddrcasn DDR Sdram Supported Ddri 16-bit Sdram Configurations Supported Ddri 32-bit Sdram ConfigurationsSupported Ddrii 32-bit Sdram Configurations Sizea Address Size Leaf Select Total Supported Ddrii 16-bit Sdram ConfigurationsDDRII/DDRI Rcomp and Slew Resistances Pin Requirements Technology Arrangement Banks Ddrii OCD Pin Requirements DDR-II Symbol Parameter Units Min MaxDDR Clock Timings DDR Sdram Write Timings DDRII-400 MHz Interface -- Signal Timings Symbol Parameter Minimum Nominal Maximum Units Timing Relationships DDR II/I Sdram Interface -- Signal TimingsSymbol Parameter Minimum Nom Maximum Units Printed Circuit Board Layer Stackup Group Signal Name Length mil Signal Package Lengths Sheet 1Timing Relationships Signal Package Lengths Sheet 2 Signal Package Lengths Sheet 3 Clock Group Data and Control Groups Parameter Definition Ddrii Data and Control Signal Group Routing Guidelines DCB70/DDRCB70, DDQ310 / DDRDQ310 Ddrii Command Signal Group Routing Guidelines Signal Group Members § §